mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
f51cdaf191
Currently, 83xx, 86xx, and 85xx have a lot of duplicated code dedicated to defining and manipulating the LBC registers. Merge this into a single spot. To do this, we have to decide on a common name for the data structure that holds the lbc registers - it will now be known as fsl_lbc_t, and we adopt a common name for the immap layouts that include the lbc - this was previously known as either im_lbc or lbus; use the former. In addition, create accessors for the BR/OR regs that use in/out_be32 and use those instead of the mismash of access methods currently in play. I have done a successful ppc build all and tested a board or two from each processor family. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Acked-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
30 lines
824 B
C
30 lines
824 B
C
/*
|
|
* Copyright 2004, 2007 Freescale Semiconductor.
|
|
* Copyright(c) 2003 Motorola Inc.
|
|
*/
|
|
|
|
#ifndef __MPC85xx_H__
|
|
#define __MPC85xx_H__
|
|
|
|
/* define for common ppc_asm.tmpl */
|
|
#define EXC_OFF_SYS_RESET 0x100 /* System reset */
|
|
#define _START_OFFSET 0
|
|
|
|
#if defined(CONFIG_E500)
|
|
#include <e500.h>
|
|
#endif
|
|
|
|
/*
|
|
* SCCR - System Clock Control Register, 9-8
|
|
*/
|
|
#define SCCR_CLPD 0x00000004 /* CPM Low Power Disable */
|
|
#define SCCR_DFBRG_MSK 0x00000003 /* Division by BRGCLK Mask */
|
|
#define SCCR_DFBRG_SHIFT 0
|
|
|
|
#define SCCR_DFBRG00 0x00000000 /* BRGCLK division by 4 */
|
|
#define SCCR_DFBRG01 0x00000001 /* BRGCLK div by 16 (normal) */
|
|
#define SCCR_DFBRG10 0x00000002 /* BRGCLK division by 64 */
|
|
#define SCCR_DFBRG11 0x00000003 /* BRGCLK division by 256 */
|
|
|
|
#endif /* __MPC85xx_H__ */
|