mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-05 02:36:39 +09:00
25ddd1fb0a
CONFIG_SYS_GBL_DATA_SIZE has always been just a bad workarond for not being able to use "sizeof(struct global_data)" in assembler files. Recent experience has shown that manual synchronization is not reliable enough. This patch renames CONFIG_SYS_GBL_DATA_SIZE into GENERATED_GBL_DATA_SIZE which gets automatically generated by the asm-offsets tool. In the result, all definitions of this value can be deleted from the board config files. We have to make sure that all files that reference such data include the new <asm-offsets.h> file. No other changes have been done yet, but it is obvious that similar changes / simplifications can be done for other, related macro definitions as well. Signed-off-by: Wolfgang Denk <wd@denx.de> Acked-by: Kumar Gala <galak@kernel.crashing.org>
430 lines
17 KiB
C
430 lines
17 KiB
C
/*
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* (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/************************************************************************
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* 1 january 2005 Alain Saurel <asaurel@amcc.com>
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* Adapted to current Das U-Boot source
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***********************************************************************/
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/************************************************************************
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* yucca.h - configuration for AMCC 440SPe Ref (yucca)
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***********************************************************************/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*-----------------------------------------------------------------------
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* High Level Configuration Options
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*----------------------------------------------------------------------*/
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#define CONFIG_4xx 1 /* ... PPC4xx family */
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#define CONFIG_440 1 /* ... PPC440 family */
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#define CONFIG_440SPE 1 /* Specifc SPe support */
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#define CONFIG_440SPE_REVA 1 /* Support old Rev A. */
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
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#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
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#define EXTCLK_33_33 33333333
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#define EXTCLK_66_66 66666666
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#define EXTCLK_50 50000000
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#define EXTCLK_83 83333333
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#define CONFIG_SYS_TEXT_BASE 0xfffb0000
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/*
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* Include common defines/options for all AMCC eval boards
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*/
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#define CONFIG_HOSTNAME yucca
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#include "amcc-common.h"
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#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
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#undef CONFIG_SHOW_BOOT_PROGRESS
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#undef CONFIG_STRESS
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/*-----------------------------------------------------------------------
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* Base addresses -- Note these are effective addresses where the
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* actual resources get mapped (not physical addresses)
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*----------------------------------------------------------------------*/
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#define CONFIG_SYS_FLASH_BASE 0xfff00000 /* start of FLASH */
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#define CONFIG_SYS_ISRAM_BASE 0x90000000 /* internal SRAM */
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#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped PCI memory */
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#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
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#define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE
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#define CONFIG_SYS_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */
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#define CONFIG_SYS_PCIE_MEMSIZE 0x08000000 /* smallest incr for PCIe port */
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#define CONFIG_SYS_PCIE_BASE 0xe0000000 /* PCIe UTL regs */
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#define CONFIG_SYS_PCIE0_CFGBASE 0xc0000000
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#define CONFIG_SYS_PCIE1_CFGBASE 0xc1000000
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#define CONFIG_SYS_PCIE2_CFGBASE 0xc2000000
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#define CONFIG_SYS_PCIE0_XCFGBASE 0xc3000000
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#define CONFIG_SYS_PCIE1_XCFGBASE 0xc3001000
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#define CONFIG_SYS_PCIE2_XCFGBASE 0xc3002000
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/* base address of inbound PCIe window */
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#define CONFIG_SYS_PCIE_INBOUND_BASE 0x0000000400000000ULL
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/* System RAM mapped to PCI space */
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#define CONFIG_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE
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#define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE
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#define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
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#define CONFIG_SYS_FPGA_BASE 0xe2000000 /* epld */
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#define CONFIG_SYS_OPER_FLASH 0xe7000000 /* SRAM - OPER Flash */
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/* #define CONFIG_SYS_NVRAM_BASE_ADDR 0x08000000 */
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/*-----------------------------------------------------------------------
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* Initial RAM & stack pointer (placed in internal SRAM)
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*----------------------------------------------------------------------*/
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#define CONFIG_SYS_TEMP_STACK_OCM 1
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#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE
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#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */
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#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
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/*-----------------------------------------------------------------------
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* Serial Port
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*----------------------------------------------------------------------*/
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#define CONFIG_CONS_INDEX 1 /* Use UART0 */
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#undef CONFIG_SYS_EXT_SERIAL_CLOCK
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/* #define CONFIG_SYS_EXT_SERIAL_CLOCK (1843200 * 6) */ /* Ext clk @ 11.059 MHz */
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/*-----------------------------------------------------------------------
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* DDR SDRAM
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*----------------------------------------------------------------------*/
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#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
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#define SPD_EEPROM_ADDRESS {0x53, 0x52} /* SPD i2c spd addresses*/
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#define CONFIG_DDR_ECC 1 /* with ECC support */
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/*-----------------------------------------------------------------------
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* I2C
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*----------------------------------------------------------------------*/
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#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
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#define IIC0_BOOTPROM_ADDR 0x50
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#define IIC0_ALT_BOOTPROM_ADDR 0x54
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/* Don't probe these addrs */
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#define CONFIG_SYS_I2C_NOPROBES {0x50, 0x52, 0x53, 0x54}
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/* #if defined(CONFIG_CMD_EEPROM) */
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/* #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 */ /* I2C boot EEPROM */
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
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/* #endif */
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/*-----------------------------------------------------------------------
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* Environment
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*----------------------------------------------------------------------*/
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/* #define CONFIG_SYS_NVRAM_SIZE (0x2000 - 8) */ /* NVRAM size(8k)- RTC regs */
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#undef CONFIG_ENV_IS_IN_NVRAM /* ... not in NVRAM */
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#define CONFIG_ENV_IS_IN_FLASH 1 /* Environment uses flash */
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#undef CONFIG_ENV_IS_IN_EEPROM /* ... not in EEPROM */
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#define CONFIG_ENV_OVERWRITE 1
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/*
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* Default environment variables
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*/
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#define CONFIG_EXTRA_ENV_SETTINGS \
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CONFIG_AMCC_DEF_ENV \
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CONFIG_AMCC_DEF_ENV_PPC \
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CONFIG_AMCC_DEF_ENV_NOR_UPD \
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"kernel_addr=E7F10000\0" \
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"ramdisk_addr=E7F20000\0" \
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"pciconfighost=1\0" \
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"pcie_mode=RP:EP:EP\0" \
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""
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/*
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* Commands additional to the ones defined in amcc-common.h
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*/
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_SDRAM
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#define CONFIG_IBM_EMAC4_V4 1
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#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
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#define CONFIG_HAS_ETH0
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#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
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#define CONFIG_PHY_RESET_DELAY 1000
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#define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */
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#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
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/*-----------------------------------------------------------------------
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* FLASH related
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*----------------------------------------------------------------------*/
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#define CONFIG_SYS_MAX_FLASH_BANKS 3 /* number of banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */
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#undef CONFIG_SYS_FLASH_CHECKSUM
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#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#define CONFIG_SYS_FLASH_ADDR0 0x5555
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#define CONFIG_SYS_FLASH_ADDR1 0x2aaa
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#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char
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#define CONFIG_SYS_FLASH_2ND_16BIT_DEV 1 /* evb440SPe has 8 and 16bit device */
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#define CONFIG_SYS_FLASH_2ND_ADDR 0xe7c00000 /* evb440SPe has 8 and 16bit device*/
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#ifdef CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
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#define CONFIG_ENV_ADDR 0xfffa0000
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/* #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) */
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#define CONFIG_ENV_SIZE 0x10000 /* Size of Environment vars */
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#endif /* CONFIG_ENV_IS_IN_FLASH */
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/*-----------------------------------------------------------------------
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* PCI stuff
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*-----------------------------------------------------------------------
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*/
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/* General PCI */
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#define CONFIG_PCI /* include pci support */
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#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
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#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
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#define CONFIG_PCI_CONFIG_HOST_BRIDGE
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/* Board-specific PCI */
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#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */
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#undef CONFIG_SYS_PCI_MASTER_INIT
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#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
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#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
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/* #define CONFIG_SYS_PCI_SUBSYS_ID CONFIG_SYS_PCI_SUBSYS_DEVICEID */
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/*
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* NETWORK Support (PCI):
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*/
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/* Support for Intel 82557/82559/82559ER chips. */
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#define CONFIG_EEPRO100
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/* FB Divisor selection */
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#define FPGA_FB_DIV_6 6
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#define FPGA_FB_DIV_10 10
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#define FPGA_FB_DIV_12 12
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#define FPGA_FB_DIV_20 20
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/* VCO Divisor selection */
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#define FPGA_VCO_DIV_4 4
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#define FPGA_VCO_DIV_6 6
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#define FPGA_VCO_DIV_8 8
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#define FPGA_VCO_DIV_10 10
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/*----------------------------------------------------------------------------+
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| FPGA registers and bit definitions
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+----------------------------------------------------------------------------*/
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/* PowerPC 440SPe Board FPGA is reached with physical address 0x1 E2000000. */
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/* TLB initialization makes it correspond to logical address 0xE2000000. */
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/* => Done init_chip.s in bootlib */
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#define FPGA_REG_BASE_ADDR 0xE2000000
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#define FPGA_GPIO_BASE_ADDR 0xE2010000
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#define FPGA_INT_BASE_ADDR 0xE2020000
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/*----------------------------------------------------------------------------+
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| Display
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+----------------------------------------------------------------------------*/
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#define PPC440SPE_DISPLAY FPGA_REG_BASE_ADDR
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#define PPC440SPE_DISPLAY_D8 (FPGA_REG_BASE_ADDR+0x06)
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#define PPC440SPE_DISPLAY_D4 (FPGA_REG_BASE_ADDR+0x04)
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#define PPC440SPE_DISPLAY_D2 (FPGA_REG_BASE_ADDR+0x02)
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#define PPC440SPE_DISPLAY_D1 (FPGA_REG_BASE_ADDR+0x00)
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/*define WRITE_DISPLAY_DIGIT(n) IOREG8(FPGA_REG_BASE_ADDR + (2*n))*/
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/*#define IOREG8(addr) *((volatile unsigned char *)(addr))*/
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/*----------------------------------------------------------------------------+
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| ethernet/reset/boot Register 1
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+----------------------------------------------------------------------------*/
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#define FPGA_REG10 (FPGA_REG_BASE_ADDR+0x10)
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#define FPGA_REG10_10MHZ_ENABLE 0x8000
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#define FPGA_REG10_100MHZ_ENABLE 0x4000
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#define FPGA_REG10_GIGABIT_ENABLE 0x2000
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#define FPGA_REG10_FULL_DUPLEX 0x1000 /* force Full Duplex*/
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#define FPGA_REG10_RESET_ETH 0x0800
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#define FPGA_REG10_AUTO_NEG_DIS 0x0400
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#define FPGA_REG10_INTP_ETH 0x0200
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#define FPGA_REG10_RESET_HISR 0x0080
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#define FPGA_REG10_ENABLE_DISPLAY 0x0040
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#define FPGA_REG10_RESET_SDRAM 0x0020
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#define FPGA_REG10_OPER_BOOT 0x0010
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#define FPGA_REG10_SRAM_BOOT 0x0008
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#define FPGA_REG10_SMALL_BOOT 0x0004
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#define FPGA_REG10_FORCE_COLA 0x0002
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#define FPGA_REG10_COLA_MANUAL 0x0001
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#define FPGA_REG10_SDRAM_ENABLE 0x0020
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#define FPGA_REG10_ENET_ENCODE2(n) ((((unsigned long)(n))&0x0F)<<4) /*from ocotea ?*/
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#define FPGA_REG10_ENET_DECODE2(n) ((((unsigned long)(n))>>4)&0x0F) /*from ocotea ?*/
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/*----------------------------------------------------------------------------+
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| MUX control
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+----------------------------------------------------------------------------*/
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#define FPGA_REG12 (FPGA_REG_BASE_ADDR+0x12)
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#define FPGA_REG12_EBC_CTL 0x8000
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#define FPGA_REG12_UART1_CTS_RTS 0x4000
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#define FPGA_REG12_UART0_RX_ENABLE 0x2000
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#define FPGA_REG12_UART1_RX_ENABLE 0x1000
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#define FPGA_REG12_UART2_RX_ENABLE 0x0800
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#define FPGA_REG12_EBC_OUT_ENABLE 0x0400
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#define FPGA_REG12_GPIO0_OUT_ENABLE 0x0200
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#define FPGA_REG12_GPIO1_OUT_ENABLE 0x0100
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#define FPGA_REG12_GPIO_SELECT 0x0010
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#define FPGA_REG12_GPIO_CHREG 0x0008
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#define FPGA_REG12_GPIO_CLK_CHREG 0x0004
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#define FPGA_REG12_GPIO_OETRI 0x0002
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#define FPGA_REG12_EBC_ERROR 0x0001
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/*----------------------------------------------------------------------------+
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| PCI Clock control
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+----------------------------------------------------------------------------*/
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#define FPGA_REG16 (FPGA_REG_BASE_ADDR+0x16)
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#define FPGA_REG16_PCI_CLK_CTL0 0x8000
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#define FPGA_REG16_PCI_CLK_CTL1 0x4000
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#define FPGA_REG16_PCI_CLK_CTL2 0x2000
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#define FPGA_REG16_PCI_CLK_CTL3 0x1000
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#define FPGA_REG16_PCI_CLK_CTL4 0x0800
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#define FPGA_REG16_PCI_CLK_CTL5 0x0400
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#define FPGA_REG16_PCI_CLK_CTL6 0x0200
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#define FPGA_REG16_PCI_CLK_CTL7 0x0100
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#define FPGA_REG16_PCI_CLK_CTL8 0x0080
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#define FPGA_REG16_PCI_CLK_CTL9 0x0040
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#define FPGA_REG16_PCI_EXT_ARB0 0x0020
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#define FPGA_REG16_PCI_MODE_1 0x0010
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#define FPGA_REG16_PCI_TARGET_MODE 0x0008
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#define FPGA_REG16_PCI_INTP_MODE 0x0004
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/* FB1 Divisor selection */
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#define FPGA_REG16_FB2_DIV_MASK 0x1000
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#define FPGA_REG16_FB2_DIV_LOW 0x0000
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#define FPGA_REG16_FB2_DIV_HIGH 0x1000
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/* FB2 Divisor selection */
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/* S3 switch on Board */
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#define FPGA_REG16_FB1_DIV_MASK 0x2000
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#define FPGA_REG16_FB1_DIV_LOW 0x0000
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#define FPGA_REG16_FB1_DIV_HIGH 0x2000
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/* PCI0 Clock Selection */
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/* S3 switch on Board */
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#define FPGA_REG16_PCI0_CLK_MASK 0x0c00
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#define FPGA_REG16_PCI0_CLK_33_33 0x0000
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#define FPGA_REG16_PCI0_CLK_66_66 0x0800
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#define FPGA_REG16_PCI0_CLK_100 0x0400
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#define FPGA_REG16_PCI0_CLK_133_33 0x0c00
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/* VCO Divisor selection */
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/* S3 switch on Board */
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#define FPGA_REG16_VCO_DIV_MASK 0xc000
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#define FPGA_REG16_VCO_DIV_4 0x0000
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#define FPGA_REG16_VCO_DIV_8 0x4000
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#define FPGA_REG16_VCO_DIV_6 0x8000
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#define FPGA_REG16_VCO_DIV_10 0xc000
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/* Master Clock Selection */
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/* S3, S4 switches on Board */
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#define FPGA_REG16_MASTER_CLK_MASK 0x01c0
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#define FPGA_REG16_MASTER_CLK_EXT 0x0000
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#define FPGA_REG16_MASTER_CLK_66_66 0x0040
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#define FPGA_REG16_MASTER_CLK_50 0x0080
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#define FPGA_REG16_MASTER_CLK_33_33 0x00c0
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#define FPGA_REG16_MASTER_CLK_25 0x0100
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/*----------------------------------------------------------------------------+
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| PCI Miscellaneous
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+----------------------------------------------------------------------------*/
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#define FPGA_REG18 (FPGA_REG_BASE_ADDR+0x18)
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#define FPGA_REG18_PCI_PRSNT1 0x8000
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#define FPGA_REG18_PCI_PRSNT2 0x4000
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#define FPGA_REG18_PCI_INTA 0x2000
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#define FPGA_REG18_PCI_SLOT0_INTP 0x1000
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#define FPGA_REG18_PCI_SLOT1_INTP 0x0800
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#define FPGA_REG18_PCI_SLOT2_INTP 0x0400
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#define FPGA_REG18_PCI_SLOT3_INTP 0x0200
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#define FPGA_REG18_PCI_PCI0_VC 0x0100
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#define FPGA_REG18_PCI_PCI0_VTH1 0x0080
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#define FPGA_REG18_PCI_PCI0_VTH2 0x0040
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#define FPGA_REG18_PCI_PCI0_VTH3 0x0020
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/*----------------------------------------------------------------------------+
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| PCIe Miscellaneous
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+----------------------------------------------------------------------------*/
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#define FPGA_REG1A (FPGA_REG_BASE_ADDR+0x1A)
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#define FPGA_REG1A_PE0_GLED 0x8000
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#define FPGA_REG1A_PE1_GLED 0x4000
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#define FPGA_REG1A_PE2_GLED 0x2000
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#define FPGA_REG1A_PE0_YLED 0x1000
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#define FPGA_REG1A_PE1_YLED 0x0800
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#define FPGA_REG1A_PE2_YLED 0x0400
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#define FPGA_REG1A_PE0_PWRON 0x0200
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#define FPGA_REG1A_PE1_PWRON 0x0100
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#define FPGA_REG1A_PE2_PWRON 0x0080
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#define FPGA_REG1A_PE0_REFCLK_ENABLE 0x0040
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#define FPGA_REG1A_PE1_REFCLK_ENABLE 0x0020
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#define FPGA_REG1A_PE2_REFCLK_ENABLE 0x0010
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#define FPGA_REG1A_PE_SPREAD0 0x0008
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#define FPGA_REG1A_PE_SPREAD1 0x0004
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#define FPGA_REG1A_PE_SELSOURCE_0 0x0002
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#define FPGA_REG1A_PE_SELSOURCE_1 0x0001
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#define FPGA_REG1A_GLED_ENCODE(n) (FPGA_REG1A_PE0_GLED >> (n))
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#define FPGA_REG1A_YLED_ENCODE(n) (FPGA_REG1A_PE0_YLED >> (n))
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#define FPGA_REG1A_PWRON_ENCODE(n) (FPGA_REG1A_PE0_PWRON >> (n))
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#define FPGA_REG1A_REFCLK_ENCODE(n) (FPGA_REG1A_PE0_REFCLK_ENABLE >> (n))
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/*----------------------------------------------------------------------------+
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| PCIe Miscellaneous
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+----------------------------------------------------------------------------*/
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#define FPGA_REG1C (FPGA_REG_BASE_ADDR+0x1C)
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#define FPGA_REG1C_PE0_ROOTPOINT 0x8000
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#define FPGA_REG1C_PE1_ENDPOINT 0x4000
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#define FPGA_REG1C_PE2_ENDPOINT 0x2000
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#define FPGA_REG1C_PE0_PRSNT 0x1000
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#define FPGA_REG1C_PE1_PRSNT 0x0800
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#define FPGA_REG1C_PE2_PRSNT 0x0400
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#define FPGA_REG1C_PE0_WAKE 0x0080
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#define FPGA_REG1C_PE1_WAKE 0x0040
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#define FPGA_REG1C_PE2_WAKE 0x0020
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#define FPGA_REG1C_PE0_PERST 0x0010
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#define FPGA_REG1C_PE1_PERST 0x0008
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#define FPGA_REG1C_PE2_PERST 0x0004
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#define FPGA_REG1C_ROOTPOINT_ENCODE(n) (FPGA_REG1C_PE0_ROOTPOINT >> (n))
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#define FPGA_REG1C_PERST_ENCODE(n) (FPGA_REG1C_PE0_PERST >> (n))
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/*----------------------------------------------------------------------------+
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| Defines
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+----------------------------------------------------------------------------*/
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#define PERIOD_133_33MHZ 7500 /* 7,5ns */
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#define PERIOD_100_00MHZ 10000 /* 10ns */
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#define PERIOD_83_33MHZ 12000 /* 12ns */
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#define PERIOD_75_00MHZ 13333 /* 13,333ns */
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#define PERIOD_66_66MHZ 15000 /* 15ns */
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#define PERIOD_50_00MHZ 20000 /* 20ns */
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#define PERIOD_33_33MHZ 30000 /* 30ns */
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#define PERIOD_25_00MHZ 40000 /* 40ns */
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#endif /* __CONFIG_H */
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