mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-05 02:36:39 +09:00
25ddd1fb0a
CONFIG_SYS_GBL_DATA_SIZE has always been just a bad workarond for not being able to use "sizeof(struct global_data)" in assembler files. Recent experience has shown that manual synchronization is not reliable enough. This patch renames CONFIG_SYS_GBL_DATA_SIZE into GENERATED_GBL_DATA_SIZE which gets automatically generated by the asm-offsets tool. In the result, all definitions of this value can be deleted from the board config files. We have to make sure that all files that reference such data include the new <asm-offsets.h> file. No other changes have been done yet, but it is obvious that similar changes / simplifications can be done for other, related macro definitions as well. Signed-off-by: Wolfgang Denk <wd@denx.de> Acked-by: Kumar Gala <galak@kernel.crashing.org>
431 lines
15 KiB
C
431 lines
15 KiB
C
/*
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* (C) Copyright 2001
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2002
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* Gregory E. Allen, gallen@arlut.utexas.edu
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* Matthew E. Karger, karger@arlut.utexas.edu
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* Applied Research Laboratories, The University of Texas at Austin
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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*
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* Configuration settings for the utx8245 board.
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*
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*/
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/* ------------------------------------------------------------------------- */
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_MPC824X 1
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#define CONFIG_MPC8245 1
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#define CONFIG_UTX8245 1
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#define CONFIG_SYS_TEXT_BASE 0xFFF00000
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#define DEBUG 1
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#define CONFIG_IDENT_STRING " [UTX5] "
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_BAUDRATE 57600
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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#define CONFIG_BOOTDELAY 2
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#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n", bootdelay
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#define CONFIG_BOOTCOMMAND "run nfsboot" /* autoboot command */
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#define CONFIG_BOOTARGS "root=/dev/ram console=ttyS0,57600" /* RAMdisk */
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#define CONFIG_ETHADDR 00:AA:00:14:00:05 /* UTX5 */
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#define CONFIG_SERVERIP 10.8.17.105 /* Spree */
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#define CONFIG_SYS_TFTP_LOADADDR 10000
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"kernel_addr=FFA00000\0" \
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"ramdisk_addr=FF800000\0" \
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"u-boot_startaddr=FFB00000\0" \
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"u-boot_endaddr=FFB2FFFF\0" \
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"nfsargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/nfs rw \
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nfsroot=${nfsrootip}:${rootpath} ip=dhcp\0" \
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"ramargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/ram0\0" \
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"smargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/mtdblock1 ro\0" \
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"fwargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/sda2 ro\0" \
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"nfsboot=run nfsargs;bootm ${kernel_addr}\0" \
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"ramboot=run ramargs;bootm ${kernel_addr} ${ramdisk_addr}\0" \
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"smboot=run smargs;bootm ${kernel_addr} ${ramdisk_addr}\0" \
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"fwboot=run fwargs;bootm ${kernel_addr} ${ramdisk_addr}\0" \
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"update_u-boot=tftp ${loadaddr} /bdi2000/u-boot.bin;protect off \
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${u-boot_startaddr} ${u-boot_endaddr};era ${u-boot_startaddr} \
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${u-boot_endaddr};cp.b ${loadaddr} ${u-boot_startaddr} ${filesize};\
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protect on ${u-boot_startaddr} ${u-boot_endaddr}"
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#define CONFIG_ENV_OVERWRITE
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_BDI
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_FLASH
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#define CONFIG_CMD_MEMORY
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#define CONFIG_CMD_SAVEENV
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#define CONFIG_CMD_CONSOLE
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#define CONFIG_CMD_LOADS
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#define CONFIG_CMD_LOADB
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#define CONFIG_CMD_IMI
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#define CONFIG_CMD_CACHE
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#define CONFIG_CMD_REGINFO
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#define CONFIG_CMD_NET
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_DATE
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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/* Print Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */
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/*-----------------------------------------------------------------------
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* PCI configuration
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_PCI /* include pci support */
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#undef CONFIG_PCI_PNP
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#define CONFIG_PCI_SCAN_SHOW
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#define CONFIG_NET_MULTI
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#define CONFIG_EEPRO100
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#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
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#define CONFIG_EEPRO100_SROM_WRITE
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#define PCI_ENET0_IOADDR 0xF0000000
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#define PCI_ENET0_MEMADDR 0xF0000000
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#define PCI_FIREWIRE_IOADDR 0xF1000000
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#define PCI_FIREWIRE_MEMADDR 0xF1000000
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/*
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#define PCI_ENET0_IOADDR 0xFE000000
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#define PCI_ENET0_MEMADDR 0x80000000
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#define PCI_FIREWIRE_IOADDR 0x81000000
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#define PCI_FIREWIRE_MEMADDR 0x81000000
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*/
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
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*/
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_MAX_RAM_SIZE 0x10000000 /* 256MB */
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/*#define CONFIG_SYS_VERY_BIG_RAM 1 */
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/* FLASH_BASE is FF800000, with 4MB on RCS0, but the reset vector
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* is actually located at FFF00100. Therefore, U-Boot is
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* physically located at 0xFFB0_0000, but is also mirrored at
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* 0xFFF0_0000.
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*/
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#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
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#define CONFIG_SYS_EUMB_ADDR 0xFC000000
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
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#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
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/*#define CONFIG_SYS_DRAM_TEST 1 */
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#define CONFIG_SYS_MEMTEST_START 0x00003000 /* memtest works on 0...256 MB */
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#define CONFIG_SYS_MEMTEST_END 0x0ff8ffa7 /* in SDRAM, skips exception */
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/* vectors and U-Boot */
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/*--------------------------------------------------------------------
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* Definitions for initial stack pointer and data area
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*------------------------------------------------------------------*/
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#define CONFIG_SYS_INIT_DATA_SIZE 128 /* Size in bytes reserved for */
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/* initial data */
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#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
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#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
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#define CONFIG_SYS_INIT_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_DATA_SIZE)
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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/*--------------------------------------------------------------------
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* NS16550 Configuration
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*------------------------------------------------------------------*/
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#if (CONFIG_CONS_INDEX == 1 || CONFIG_CONS_INDEX == 2)
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# define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
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#else
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# define CONFIG_SYS_NS16550_CLK 33000000
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#endif
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_EUMB_ADDR + 0x4500)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_EUMB_ADDR + 0x4600)
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#define CONFIG_SYS_NS16550_COM3 0xFF000000
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#define CONFIG_SYS_NS16550_COM4 0xFF000008
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/*--------------------------------------------------------------------
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* Low Level Configuration Settings
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* (address mappings, register initial values, etc.)
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* You should know what you are doing if you make changes here.
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* For the detail description refer to the MPC8240 user's manual.
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*------------------------------------------------------------------*/
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#define CONFIG_SYS_CLK_FREQ 33000000
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#define CONFIG_SYS_HZ 1000
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/*#define CONFIG_SYS_ETH_DEV_FN 0x7800 */
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/*#define CONFIG_SYS_ETH_IOBASE 0x00104000 */
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/*--------------------------------------------------------------------
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* I2C Configuration
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*------------------------------------------------------------------*/
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#if 1
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#define CONFIG_HARD_I2C 1 /* To enable I2C support */
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#undef CONFIG_SOFT_I2C /* I2C bit-banged */
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#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CONFIG_SYS_I2C_SLAVE 0x7F
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#endif
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#define CONFIG_RTC_PCF8563 1 /* enable I2C support for */
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/* Philips PCF8563 RTC */
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#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Philips PCF8563 RTC address */
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/*--------------------------------------------------------------------
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* Memory Control Configuration Register values
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* - see sec. 4.12 of MPC8245 UM
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*------------------------------------------------------------------*/
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/**** MCCR1 ****/
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#define CONFIG_SYS_ROMNAL 0
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#define CONFIG_SYS_ROMFAL 10 /* (tacc=70ns)*mem_freq - 2,
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mem_freq = 100MHz */
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#define CONFIG_SYS_BANK7_ROW 0 /* SDRAM bank 7-0 row address */
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#define CONFIG_SYS_BANK6_ROW 0 /* bit count */
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#define CONFIG_SYS_BANK5_ROW 0
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#define CONFIG_SYS_BANK4_ROW 0
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#define CONFIG_SYS_BANK3_ROW 0
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#define CONFIG_SYS_BANK2_ROW 0
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#define CONFIG_SYS_BANK1_ROW 2
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#define CONFIG_SYS_BANK0_ROW 2
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/**** MCCR2, refresh interval clock cycles ****/
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#define CONFIG_SYS_REFINT 480 /* 33 MHz SDRAM clock was 480 */
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/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. */
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#define CONFIG_SYS_BSTOPRE 1023 /* burst to precharge[0..9], */
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/* sets open page interval */
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/**** MCCR3 ****/
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#define CONFIG_SYS_REFREC 7 /* Refresh to activate interval, trc */
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/**** MCCR4 ****/
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#define CONFIG_SYS_PRETOACT 2 /* trp */
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#define CONFIG_SYS_ACTTOPRE 7 /* trcd + (burst length - 1) + trdl */
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#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */
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#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type, sequential */
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#define CONFIG_SYS_ACTORW 2 /* trcd min */
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#define CONFIG_SYS_DBUS_SIZE2 1 /* set for 8-bit RCS1, clear for 32,64 */
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#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
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#define CONFIG_SYS_EXTROM 0 /* we don't need extended ROM space */
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#define CONFIG_SYS_REGDIMM 0
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/* calculate according to formula in sec. 6-22 of 8245 UM */
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#define CONFIG_SYS_PGMAX 50 /* how long the 8245 retains the */
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/* currently accessed page in memory */
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/* was 45 */
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#define CONFIG_SYS_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay - note */
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/* bits 7,6, and 3-0 MUST be 0 */
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#if 0
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#define CONFIG_SYS_DLL_MAX_DELAY 0x04
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#else
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#define CONFIG_SYS_DLL_MAX_DELAY 0
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#endif
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#if 0 /* need for 33MHz SDRAM */
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#define CONFIG_SYS_DLL_EXTEND 0x80
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#else
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#define CONFIG_SYS_DLL_EXTEND 0
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#endif
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#define CONFIG_SYS_PCI_HOLD_DEL 0x20
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/* Memory bank settings.
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* Only bits 20-29 are actually used from these values to set the
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* start/end addresses. The upper two bits will always be 0, and the lower
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* 20 bits will be 0x00000 for a start address, or 0xfffff for an end
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* address. Refer to the MPC8245 user manual.
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*/
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#define CONFIG_SYS_BANK0_START 0x00000000
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#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE/2 - 1)
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#define CONFIG_SYS_BANK0_ENABLE 1
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#define CONFIG_SYS_BANK1_START CONFIG_SYS_MAX_RAM_SIZE/2
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#define CONFIG_SYS_BANK1_END (CONFIG_SYS_MAX_RAM_SIZE - 1)
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#define CONFIG_SYS_BANK1_ENABLE 1
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#define CONFIG_SYS_BANK2_START 0x3ff00000 /* not available in this design */
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#define CONFIG_SYS_BANK2_END 0x3fffffff
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#define CONFIG_SYS_BANK2_ENABLE 0
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#define CONFIG_SYS_BANK3_START 0x3ff00000
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#define CONFIG_SYS_BANK3_END 0x3fffffff
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#define CONFIG_SYS_BANK3_ENABLE 0
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#define CONFIG_SYS_BANK4_START 0x3ff00000
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#define CONFIG_SYS_BANK4_END 0x3fffffff
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#define CONFIG_SYS_BANK4_ENABLE 0
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#define CONFIG_SYS_BANK5_START 0x3ff00000
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#define CONFIG_SYS_BANK5_END 0x3fffffff
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#define CONFIG_SYS_BANK5_ENABLE 0
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#define CONFIG_SYS_BANK6_START 0x3ff00000
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#define CONFIG_SYS_BANK6_END 0x3fffffff
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#define CONFIG_SYS_BANK6_ENABLE 0
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#define CONFIG_SYS_BANK7_START 0x3ff00000
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#define CONFIG_SYS_BANK7_END 0x3fffffff
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#define CONFIG_SYS_BANK7_ENABLE 0
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/*--------------------------------------------------------------------*/
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/* 4.4 - Output Driver Control Register */
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/*--------------------------------------------------------------------*/
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#define CONFIG_SYS_ODCR 0xe5
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/*--------------------------------------------------------------------*/
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/* 4.8 - Error Handling Registers */
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/*-------------------------------CONFIG_SYS_SDMODE_BURSTLEN-------------------------------------*/
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#define CONFIG_SYS_ERRENR1 0x11 /* enable SDRAM refresh overflow error */
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/* SDRAM 0-256 MB */
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#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
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/*#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_CACHEINHIBIT) */
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#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
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/* stack in dcache */
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#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
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#define CONFIG_SYS_IBAT2L (CONFIG_SYS_SDRAM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT2U (CONFIG_SYS_SDRAM_BASE + 0x10000000| BATU_BL_256M | BATU_VS | BATU_VP)
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/* PCI memory */
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/*#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) */
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/*#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) */
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/*Flash, config addrs, etc. */
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#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
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#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
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#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
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#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
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#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
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#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
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#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
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#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
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#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* FLASH organization
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*----------------------------------------------------------------------*/
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#define CONFIG_SYS_FLASH_BASE 0xFF800000
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */
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/* NOTE: environment is not EMBEDDED in the u-boot code.
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It's stored in flash in its own separate sector. */
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#define CONFIG_ENV_IS_IN_FLASH 1
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#if 1 /* AMD AM29LV033C */
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#define CONFIG_SYS_MAX_FLASH_SECT 64 /* Max number of sectors in one bank */
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#define CONFIG_ENV_ADDR 0xFFBF0000 /* flash sector SA63 */
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#define CONFIG_ENV_SECT_SIZE (64*1024) /* Size of the Environment Sector */
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#else /* AMD AM29LV116D */
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#define CONFIG_SYS_MAX_FLASH_SECT 35 /* Max number of sectors in one bank */
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#define CONFIG_ENV_ADDR 0xFF9FA000 /* flash sector SA33 */
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#define CONFIG_ENV_SECT_SIZE (8*1024) /* Size of the Environment Sector */
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#endif /* #if */
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#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE /* Size of the Environment */
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#define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */
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#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
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#undef CONFIG_SYS_RAMBOOT
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#else
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#define CONFIG_SYS_RAMBOOT
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#endif
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CONFIG_SYS_CACHELINE_SIZE 32
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#if defined(CONFIG_CMD_KGDB)
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# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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#endif
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#endif /* __CONFIG_H */
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