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https://github.com/brain-hackers/u-boot-brain
synced 2024-07-05 02:36:39 +09:00
25ddd1fb0a
CONFIG_SYS_GBL_DATA_SIZE has always been just a bad workarond for not being able to use "sizeof(struct global_data)" in assembler files. Recent experience has shown that manual synchronization is not reliable enough. This patch renames CONFIG_SYS_GBL_DATA_SIZE into GENERATED_GBL_DATA_SIZE which gets automatically generated by the asm-offsets tool. In the result, all definitions of this value can be deleted from the board config files. We have to make sure that all files that reference such data include the new <asm-offsets.h> file. No other changes have been done yet, but it is obvious that similar changes / simplifications can be done for other, related macro definitions as well. Signed-off-by: Wolfgang Denk <wd@denx.de> Acked-by: Kumar Gala <galak@kernel.crashing.org>
427 lines
14 KiB
C
427 lines
14 KiB
C
/*
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* (C) Copyright 2006
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* Markus Klotzbuecher, DENX Software Engineering, mk@denx.de
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*
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* Configuation settings for the SPC1920 board.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __H
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#define __CONFIG_H
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#define CONFIG_SPC1920 1 /* SPC1920 board */
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#define CONFIG_MPC885 1 /* MPC885 CPU */
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#define CONFIG_SYS_TEXT_BASE 0xFFF00000
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#define CONFIG_8xx_CONS_SMC1 /* Console is on SMC1 */
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#undef CONFIG_8xx_CONS_SMC2
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#undef CONFIG_8xx_CONS_NONE
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#define CONFIG_MII
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#define CONFIG_MII_INIT 1
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#undef CONFIG_ETHER_ON_FEC1
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#define CONFIG_ETHER_ON_FEC2
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#define FEC_ENET
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#define CONFIG_FEC2_PHY 1
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#define CONFIG_BAUDRATE 19200
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/* use PLD CLK4 instead of brg */
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#define CONFIG_SYS_SPC1920_SMC1_CLK4
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#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */
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#define CONFIG_8xx_CPUCLK_DEFAULT 50000000
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#define CONFIG_SYS_8xx_CPUCLK_MIN 40000000
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#define CONFIG_SYS_8xx_CPUCLK_MAX 133000000
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#define CONFIG_SYS_RESET_ADDRESS 0xC0000000
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#define CONFIG_BOARD_EARLY_INIT_F
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#define CONFIG_LAST_STAGE_INIT
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#if 0
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#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
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#else
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#endif
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_NFSBOOTCOMMAND \
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"dhcp;" \
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"setenv bootargs root=/dev/nfs rw nfsroot=$rootpath " \
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"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \
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"bootm"
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#define CONFIG_BOOTCOMMAND \
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"setenv bootargs root=/dev/mtdblock2 rw mtdparts=phys:1280K(ROM)ro,-(root) "\
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"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \
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"bootm fe080000"
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#undef CONFIG_BOOTARGS
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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#define CONFIG_BZIP2 /* include support for bzip2 compressed images */
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_ASKENV
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_ECHO
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#define CONFIG_CMD_IMMAP
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#define CONFIG_CMD_JFFS2
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#define CONFIG_CMD_NET
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_MII
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_PROMPT "=>" /* Monitor Command Prompt */
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#define CONFIG_SYS_HUSH_PARSER
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_LOAD_ADDR 0x00100000
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#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CONFIG_SYS_BAUDRATE_TABLE { 2400, 4800, 9600, 19200 }
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/*
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* Low Level Configuration Settings
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* (address mappings, register initial values, etc.)
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* You should know what you are doing if you make changes here.
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*/
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/*-----------------------------------------------------------------------
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* Internal Memory Mapped Register
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*/
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#define CONFIG_SYS_IMMR 0xF0000000
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in DPRAM)
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*/
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#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
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#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
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*/
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#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 KB for monitor */
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#ifdef CONFIG_BZIP2
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#define CONFIG_SYS_MALLOC_LEN (2500 << 10) /* Reserve ~2.5 MB for malloc() */
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#else
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#define CONFIG_SYS_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */
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#endif /* CONFIG_BZIP2 */
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#define CONFIG_SYS_ALLOC_DPRAM 1 /* use allocation routines */
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/*
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* Flash
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*/
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/*-----------------------------------------------------------------------
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* Flash organisation
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*/
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#define CONFIG_SYS_FLASH_BASE 0xFE000000
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#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
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#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 128 /* Max num of sects on one chip */
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/* Environment is in flash */
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#define CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_SECT_SIZE 0x40000 /* We use one complete sector */
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
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#define CONFIG_ENV_OVERWRITE
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
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#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
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#ifdef CONFIG_CMD_DATE
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# define CONFIG_RTC_DS3231
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# define CONFIG_SYS_I2C_RTC_ADDR 0x68
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#endif
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/*-----------------------------------------------------------------------
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* I2C configuration
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*/
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#if defined(CONFIG_CMD_I2C)
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/* enable I2C and select the hardware/software driver */
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#undef CONFIG_HARD_I2C /* I2C with hardware support */
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#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
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#define CONFIG_SYS_I2C_SPEED 93000 /* 93 kHz is supposed to work */
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#define CONFIG_SYS_I2C_SLAVE 0xFE
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#ifdef CONFIG_SOFT_I2C
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/*
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* Software (bit-bang) I2C driver configuration
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*/
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#define PB_SCL 0x00000020 /* PB 26 */
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#define PB_SDA 0x00000010 /* PB 27 */
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#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
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#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
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#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
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#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
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#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
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else immr->im_cpm.cp_pbdat &= ~PB_SDA
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#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
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else immr->im_cpm.cp_pbdat &= ~PB_SCL
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#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
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#endif /* CONFIG_SOFT_I2C */
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#endif
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/*-----------------------------------------------------------------------
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* SYPCR - System Protection Control 11-9
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* SYPCR can only be written once after reset!
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*-----------------------------------------------------------------------
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* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
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*/
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#if defined(CONFIG_WATCHDOG)
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#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
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SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
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#else
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#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
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#endif
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/*-----------------------------------------------------------------------
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* SIUMCR - SIU Module Configuration 11-6
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*-----------------------------------------------------------------------
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* PCMCIA config., multi-function pin tri-state
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*/
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#define CONFIG_SYS_SIUMCR (SIUMCR_FRC)
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/*-----------------------------------------------------------------------
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* TBSCR - Time Base Status and Control 11-26
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*-----------------------------------------------------------------------
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* Clear Reference Interrupt Status, Timebase freezing enabled
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*/
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#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
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/*-----------------------------------------------------------------------
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* PISCR - Periodic Interrupt Status and Control 11-31
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*-----------------------------------------------------------------------
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* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
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*/
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#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
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/*-----------------------------------------------------------------------
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* SCCR - System Clock and reset Control Register 15-27
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*-----------------------------------------------------------------------
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* Set clock output, timebase and RTC source and divider,
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* power management and some other internal clocks
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*/
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#define SCCR_MASK SCCR_EBDF11
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/* #define CONFIG_SYS_SCCR SCCR_TBS */
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#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
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SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
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SCCR_DFALCD00)
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/*-----------------------------------------------------------------------
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* DER - Debug Enable Register
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*-----------------------------------------------------------------------
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* Set to zero to prevent the processor from entering debug mode
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*/
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#define CONFIG_SYS_DER 0
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/* Because of the way the 860 starts up and assigns CS0 the entire
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* address space, we have to set the memory controller differently.
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* Normally, you write the option register first, and then enable the
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* chip select by writing the base register. For CS0, you must write
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* the base register first, followed by the option register.
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*/
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/*
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* Init Memory Controller:
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*/
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/* BR0 and OR0 (FLASH) */
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#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */
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/* used to re-map FLASH both when starting from SRAM or FLASH:
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* restrict access enough to keep SRAM working (if any)
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* but not too much to meddle with FLASH accesses
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*/
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#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
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#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
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/*
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* FLASH timing:
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*/
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#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
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OR_SCY_6_CLK | OR_EHTR | OR_BI)
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#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
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#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
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#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
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/*
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* SDRAM CS1 UPMB
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*/
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_SDRAM_BASE_PRELIM CONFIG_SYS_SDRAM_BASE
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#define SDRAM_MAX_SIZE 0x4000000 /* max 64 MB */
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#define CONFIG_SYS_PRELIM_OR1_AM 0xF0000000
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/* #define CONFIG_SYS_OR1_TIMING OR_CSNT_SAM/\* | OR_G5LS /\\* *\\/ *\/ */
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#define SDRAM_TIMING OR_SCY_0_CLK /* SDRAM-Timing */
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#define CONFIG_SYS_OR1_PRELIM (CONFIG_SYS_PRELIM_OR1_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING)
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#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V)
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/* #define CONFIG_SYS_OR1_FINAL ((CONFIG_SYS_OR1_AM & OR_AM_MSK) | CONFIG_SYS_OR1_TIMING) */
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/* #define CONFIG_SYS_BR1_FINAL ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V) */
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#define CONFIG_SYS_PTB_PER_CLK ((4096 * 16 * 1000) / (4 * 64))
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#define CONFIG_SYS_PTA_PER_CLK 195
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#define CONFIG_SYS_MBMR_PTB 195
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#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV16
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#define CONFIG_SYS_MAR 0x88
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#define CONFIG_SYS_MBMR_8COL ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) | \
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MBMR_AMB_TYPE_0 | \
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MBMR_G0CLB_A10 | \
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MBMR_DSB_1_CYCL | \
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MBMR_RLFB_1X | \
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MBMR_WLFB_1X | \
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MBMR_TLFB_4X) /* 0x04804114 */ /* 0x10802114 */
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#define CONFIG_SYS_MBMR_9COL ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) | \
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MBMR_AMB_TYPE_1 | \
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MBMR_G0CLB_A10 | \
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MBMR_DSB_1_CYCL | \
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MBMR_RLFB_1X | \
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MBMR_WLFB_1X | \
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MBMR_TLFB_4X) /* 0x04804114 */ /* 0x10802114 */
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/*
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* DSP Host Port Interface CS3
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*/
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#define CONFIG_SYS_SPC1920_HPI_BASE 0x90000000
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#define CONFIG_SYS_PRELIM_OR3_AM 0xF8000000
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#define CONFIG_SYS_OR3 (CONFIG_SYS_PRELIM_OR3_AM | \
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OR_G5LS | \
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OR_SCY_0_CLK | \
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OR_BI)
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#define CONFIG_SYS_BR3 ((CONFIG_SYS_SPC1920_HPI_BASE & BR_BA_MSK) | \
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BR_MS_UPMA | \
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BR_PS_16 | \
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BR_V)
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#define CONFIG_SYS_MAMR (MAMR_GPL_A4DIS | \
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MAMR_RLFA_5X | \
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MAMR_WLFA_5X)
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#define CONFIG_SPC1920_HPI_TEST
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#ifdef CONFIG_SPC1920_HPI_TEST
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#define HPI_REG(x) (*((volatile u16 *) (CONFIG_SYS_SPC1920_HPI_BASE + x)))
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#define HPI_HPIC_1 HPI_REG(0)
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#define HPI_HPIC_2 HPI_REG(2)
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#define HPI_HPIA_1 HPI_REG(0x2000008)
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#define HPI_HPIA_2 HPI_REG(0x2000008 + 2)
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#define HPI_HPID_INC_1 HPI_REG(0x1000004)
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#define HPI_HPID_INC_2 HPI_REG(0x1000004 + 2)
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#define HPI_HPID_NOINC_1 HPI_REG(0x300000c)
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#define HPI_HPID_NOINC_2 HPI_REG(0x300000c + 2)
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#endif /* CONFIG_SPC1920_HPI_TEST */
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/*
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* Ramtron FM18L08 FRAM 32KB on CS4
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*/
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#define CONFIG_SYS_SPC1920_FRAM_BASE 0x80100000
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#define CONFIG_SYS_PRELIM_OR4_AM 0xffff8000
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#define CONFIG_SYS_OR4 (CONFIG_SYS_PRELIM_OR4_AM | \
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OR_ACS_DIV2 | \
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OR_BI | \
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OR_SCY_4_CLK | \
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OR_TRLX)
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#define CONFIG_SYS_BR4 ((CONFIG_SYS_SPC1920_FRAM_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
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/*
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* PLD CS5
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*/
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#define CONFIG_SYS_SPC1920_PLD_BASE 0x80000000
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#define CONFIG_SYS_PRELIM_OR5_AM 0xffff8000
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#define CONFIG_SYS_OR5_PRELIM (CONFIG_SYS_PRELIM_OR5_AM | \
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OR_CSNT_SAM | \
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OR_ACS_DIV1 | \
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OR_BI | \
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OR_SCY_0_CLK | \
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OR_TRLX)
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#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_SPC1920_PLD_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
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#endif /* __CONFIG_H */
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