mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-05 02:36:39 +09:00
25ddd1fb0a
CONFIG_SYS_GBL_DATA_SIZE has always been just a bad workarond for not being able to use "sizeof(struct global_data)" in assembler files. Recent experience has shown that manual synchronization is not reliable enough. This patch renames CONFIG_SYS_GBL_DATA_SIZE into GENERATED_GBL_DATA_SIZE which gets automatically generated by the asm-offsets tool. In the result, all definitions of this value can be deleted from the board config files. We have to make sure that all files that reference such data include the new <asm-offsets.h> file. No other changes have been done yet, but it is obvious that similar changes / simplifications can be done for other, related macro definitions as well. Signed-off-by: Wolfgang Denk <wd@denx.de> Acked-by: Kumar Gala <galak@kernel.crashing.org>
418 lines
12 KiB
C
418 lines
12 KiB
C
/*
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* ppmc7xx.h
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* ---------
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*
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* Wind River PPMC 7xx/74xx board configuration file.
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*
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* By Richard Danter (richard.danter@windriver.com)
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* Copyright (C) 2005 Wind River Systems
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_PPMC7XX
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/*===================================================================
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*
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* User configurable settings - Modify to your preference
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*
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*===================================================================
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*/
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/*
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* Debug
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*
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* DEBUG - Define this is you want extra debug info
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* GTREGREAD - Required to build with debug
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* do_bdinfo - Required to build with debug
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*/
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#ifdef DEBUG
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#define GTREGREAD(x) 0xFFFFFFFF
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#define do_bdinfo(a,b,c,d)
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#endif
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/*
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* CPU type
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*
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* CONFIG_7xx - We have a 750 or 755 CPU
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* CONFIG_74xx - We have a 7400 CPU
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* CONFIG_ALTIVEC - We have altivec enabled CPU (only 7400)
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* CONFIG_BUS_CLK - System bus clock in Hz
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*/
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#define CONFIG_7xx
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#undef CONFIG_74xx
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#undef CONFIG_ALTIVEC
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#define CONFIG_BUS_CLK 66000000
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#define CONFIG_SYS_TEXT_BASE 0xFFF00000
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/*
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* Monitor configuration
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*
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* List of command sets to include in shell
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*
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* The following command sets have been tested and known to work:
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*
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* CMD_CACHE - Cache control commands
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* CMD_MEMORY - Memory display, change and test commands
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* CMD_FLASH - Erase and program flash
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* CMD_ENV - Environment commands
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* CMD_RUN - Run commands stored in env vars
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* CMD_ELF - Load ELF files
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* CMD_NET - Networking/file download commands
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* CMD_PIN - ICMP Echo Request command
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* CMD_PCI - PCI Bus scanning command
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*/
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_FLASH
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#define CONFIG_CMD_SAVEENV
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#define CONFIG_CMD_RUN
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#define CONFIG_CMD_ELF
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#define CONFIG_CMD_NET
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_PCI
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#undef CONFIG_CMD_KGDB
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/*
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* Serial configuration
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*
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* CONFIG_CONS_INDEX - Serial console port number (COM1)
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* CONFIG_BAUDRATE - Serial speed
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*/
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_BAUDRATE 9600
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/*
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* PCI config
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*
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* CONFIG_PCI - Enable PCI bus
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* CONFIG_PCI_PNP - Enable Plug & Play support
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* CONFIG_PCI_SCAN_SHOW - Enable display of devices at startup
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*/
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#define CONFIG_PCI
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#define CONFIG_PCI_PNP
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#undef CONFIG_PCI_SCAN_SHOW
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/*
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* Network config
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*
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* CONFIG_NET_MULTI - Support for multiple network interfaces
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* CONFIG_EEPRO100 - Intel 8255x Ethernet Controller
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* CONFIG_EEPRO100_SROM_WRITE - Enable writing to network card ROM
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*/
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#define CONFIG_NET_MULTI
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#define CONFIG_EEPRO100
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#define CONFIG_EEPRO100_SROM_WRITE
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/*
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* Enable extra init functions
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*
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* CONFIG_MISC_INIT_F - Call pre-relocation init functions
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* CONFIG_MISC_INIT_R - Call post relocation init functions
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*/
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#undef CONFIG_MISC_INIT_F
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#define CONFIG_MISC_INIT_R
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/*
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* Boot config
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*
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* CONFIG_BOOTCOMMAND - Command(s) to execute to auto-boot
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* CONFIG_BOOTDELAY - How long to wait before auto-boot (in sec)
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*/
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#define CONFIG_BOOTCOMMAND \
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"bootp;" \
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"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
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"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
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"bootm"
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#define CONFIG_BOOTDELAY 5
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/*===================================================================
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*
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* Board configuration settings - You should not need to modify these
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*
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*===================================================================
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*/
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/*
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* Memory map
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*
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* This board runs in a standard CHRP (Map-B) configuration.
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*
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* Type Start End Size Width Chip Sel
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* ----------- ----------- ----------- ------- ------- --------
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* SDRAM 0x00000000 0x04000000 64MB 64b SDRAMCS0
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* User LED's 0x78000000 RCS3
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* UART 0x7C000000 RCS2
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* Mailbox 0xFF000000 RCS1
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* Flash 0xFFC00000 0xFFFFFFFF 4MB 64b RCS0
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*
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* Flash sectors are laid out as follows.
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*
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* Sector Start End Size Comments
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* ------- ----------- ----------- ------- -----------
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* 0 0xFFC00000 0xFFC3FFFF 256KB
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* 1 0xFFC40000 0xFFC7FFFF 256KB
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* 2 0xFFC80000 0xFFCBFFFF 256KB
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* 3 0xFFCC0000 0xFFCFFFFF 256KB
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* 4 0xFFD00000 0xFFD3FFFF 256KB
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* 5 0xFFD40000 0xFFD7FFFF 256KB
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* 6 0xFFD80000 0xFFDBFFFF 256KB
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* 7 0xFFDC0000 0xFFDFFFFF 256KB
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* 8 0xFFE00000 0xFFE3FFFF 256KB
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* 9 0xFFE40000 0xFFE7FFFF 256KB
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* 10 0xFFE80000 0xFFEBFFFF 256KB
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* 11 0xFFEC0000 0xFFEFFFFF 256KB
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* 12 0xFFF00000 0xFFF3FFFF 256KB U-Boot code here
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* 13 0xFFF40000 0xFFF7FFFF 256KB
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* 14 0xFFF80000 0xFFFBFFFF 256KB
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* 15 0xFFFC0000 0xFFFDFFFF 128KB
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* 16 0xFFFE0000 0xFFFE7FFF 32KB U-Boot env vars here
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* 17 0xFFFE8000 0xFFFEFFFF 32KB U-Boot backup copy of env vars here
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* 18 0xFFFF0000 0xFFFFFFFF 64KB
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*/
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/*
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* SDRAM config - see memory map details above.
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*
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* CONFIG_SYS_SDRAM_BASE - Start address of SDRAM, this _must_ be zero!
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* CONFIG_SYS_SDRAM_SIZE - Total size of contiguous SDRAM bank(s)
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*/
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_SDRAM_SIZE 0x04000000
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/*
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* Flash config - see memory map details above.
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*
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* CONFIG_SYS_FLASH_BASE - Start address of flash memory
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* CONFIG_SYS_FLASH_SIZE - Total size of contiguous flash mem
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* CONFIG_SYS_FLASH_ERASE_TOUT - Erase timeout in ms
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* CONFIG_SYS_FLASH_WRITE_TOUT - Write timeout in ms
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* CONFIG_SYS_MAX_FLASH_BANKS - Number of banks of flash on board
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* CONFIG_SYS_MAX_FLASH_SECT - Number of sectors in a bank
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*/
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#define CONFIG_SYS_FLASH_BASE 0xFFC00000
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#define CONFIG_SYS_FLASH_SIZE 0x00400000
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#define CONFIG_SYS_FLASH_ERASE_TOUT 250000
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#define CONFIG_SYS_FLASH_WRITE_TOUT 5000
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_SYS_MAX_FLASH_SECT 19
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/*
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* Monitor config - see memory map details above
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*
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* CONFIG_SYS_MONITOR_BASE - Base address of monitor code
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* CONFIG_SYS_MALLOC_LEN - Size of malloc pool (128KB)
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*/
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_MALLOC_LEN 0x20000
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/*
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* Command shell settings
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*
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* CONFIG_SYS_BARGSIZE - Boot Argument buffer size
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* CONFIG_SYS_BOOTMAPSZ - Size of app's mapped RAM at boot (Linux=8MB)
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* CONFIG_SYS_CBSIZE - Console Buffer (input) size
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* CONFIG_SYS_LOAD_ADDR - Default load address
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* CONFIG_SYS_LONGHELP - Provide more detailed help
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* CONFIG_SYS_MAXARGS - Number of args accepted by monitor commands
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* CONFIG_SYS_MEMTEST_START - Start address of test to run on RAM
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* CONFIG_SYS_MEMTEST_END - End address of RAM test
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* CONFIG_SYS_PBSIZE - Print Buffer (output) size
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* CONFIG_SYS_PROMPT - Prompt string
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*/
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#define CONFIG_SYS_BARGSIZE 1024
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#define CONFIG_SYS_BOOTMAPSZ 0x800000
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#define CONFIG_SYS_CBSIZE 1024
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#define CONFIG_SYS_LOAD_ADDR 0x100000
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#define CONFIG_SYS_LONGHELP
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#define CONFIG_SYS_MAXARGS 16
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#define CONFIG_SYS_MEMTEST_START 0x00040000
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#define CONFIG_SYS_MEMTEST_END 0x00040100
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#define CONFIG_SYS_PBSIZE 1024
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#define CONFIG_SYS_PROMPT "=> "
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/*
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* Environment config - see memory map details above
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*
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* CONFIG_ENV_IS_IN_FLASH - The env variables are stored in flash
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* CONFIG_ENV_ADDR - Address of the sector containing env vars
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* CONFIG_ENV_SIZE - Ammount of RAM for env vars (used to save RAM, 4KB)
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* CONFIG_ENV_SECT_SIZE - Size of sector containing env vars (32KB)
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*/
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_ADDR 0xFFFE0000
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#define CONFIG_ENV_SIZE 0x1000
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#define CONFIG_ENV_ADDR_REDUND 0xFFFE8000
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#define CONFIG_ENV_SIZE_REDUND 0x1000
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#define CONFIG_ENV_SECT_SIZE 0x8000
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/*
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* Initial RAM config
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*
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* Since the main system RAM is initialised very early, we place the INIT_RAM
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* in the main system RAM just above the exception vectors. The contents are
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* copied to top of RAM by the init code.
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*
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* CONFIG_SYS_INIT_RAM_ADDR - Address of Init RAM, above exception vect
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* CONFIG_SYS_INIT_RAM_SIZE - Size of Init RAM
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* GENERATED_GBL_DATA_SIZE - Ammount of RAM to reserve for global data
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* CONFIG_SYS_GBL_DATA_OFFSET - Start of global data, top of stack
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*/
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#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4000)
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#define CONFIG_SYS_INIT_RAM_SIZE 0x4000
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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/*
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* Initial BAT config
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*
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* BAT0 - System SDRAM
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* BAT1 - LED's and Serial Port
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* BAT2 - PCI Memory
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* BAT3 - PCI I/O including Flash Memory
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*/
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#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
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#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
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#define CONFIG_SYS_IBAT1L (0x70000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
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#define CONFIG_SYS_IBAT1U (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_DBAT1L (0x70000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_DBAT1U (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
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#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_DBAT2L (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_DBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
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#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_DBAT3L (0xF0000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_DBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
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/*
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* Cache config
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*
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* CONFIG_SYS_CACHELINE_SIZE - Size of a cache line (CPU specific)
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* CONFIG_SYS_L2 - L2 cache enabled if defined
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* L2_INIT - L2 cache init flags
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* L2_ENABLE - L2 cache enable flags
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*/
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#define CONFIG_SYS_CACHELINE_SIZE 32
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#undef CONFIG_SYS_L2
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#define L2_INIT 0
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#define L2_ENABLE 0
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/*
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* Clocks config
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*
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* CONFIG_SYS_BUS_CLK - Bus clock frequency in Hz
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* CONFIG_SYS_HZ - Decrementer freq in Hz
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*/
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#define CONFIG_SYS_BUS_CLK CONFIG_BUS_CLK
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#define CONFIG_SYS_HZ 1000
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/*
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* Serial port config
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*
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* CONFIG_SYS_BAUDRATE_TABLE - List of valid baud rates
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* CONFIG_SYS_NS16550 - Include the NS16550 driver
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* CONFIG_SYS_NS16550_SERIAL - Include the serial (wrapper) driver
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* CONFIG_SYS_NS16550_CLK - Frequency of reference clock
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* CONFIG_SYS_NS16550_REG_SIZE - 64-bit accesses to 8-bit port
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* CONFIG_SYS_NS16550_COM1 - Base address of 1st serial port
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*/
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_CLK 3686400
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#define CONFIG_SYS_NS16550_REG_SIZE -8
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#define CONFIG_SYS_NS16550_COM1 0x7C000000
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/*
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* PCI Config - Address Map B (CHRP)
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*/
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#define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000
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#define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000
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#define CONFIG_SYS_PCI_MEMORY_SIZE 0x40000000
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#define CONFIG_SYS_PCI_MEM_BUS 0x80000000
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#define CONFIG_SYS_PCI_MEM_PHYS 0x80000000
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#define CONFIG_SYS_PCI_MEM_SIZE 0x7D000000
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#define CONFIG_SYS_ISA_MEM_BUS 0x00000000
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#define CONFIG_SYS_ISA_MEM_PHYS 0xFD000000
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#define CONFIG_SYS_ISA_MEM_SIZE 0x01000000
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#define CONFIG_SYS_PCI_IO_BUS 0x00800000
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#define CONFIG_SYS_PCI_IO_PHYS 0xFE800000
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#define CONFIG_SYS_PCI_IO_SIZE 0x00400000
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#define CONFIG_SYS_ISA_IO_BUS 0x00000000
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#define CONFIG_SYS_ISA_IO_PHYS 0xFE000000
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#define CONFIG_SYS_ISA_IO_SIZE 0x00800000
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#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_ISA_IO_PHYS
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#define CONFIG_SYS_ISA_IO CONFIG_SYS_ISA_IO_PHYS
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#define CONFIG_SYS_60X_PCI_IO_OFFSET CONFIG_SYS_ISA_IO_PHYS
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/*
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* Extra init functions
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*
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* CONFIG_SYS_BOARD_ASM_INIT - Call assembly init code
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*/
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#define CONFIG_SYS_BOARD_ASM_INIT
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#endif /* __CONFIG_H */
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