mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-05 02:36:39 +09:00
25ddd1fb0a
CONFIG_SYS_GBL_DATA_SIZE has always been just a bad workarond for not being able to use "sizeof(struct global_data)" in assembler files. Recent experience has shown that manual synchronization is not reliable enough. This patch renames CONFIG_SYS_GBL_DATA_SIZE into GENERATED_GBL_DATA_SIZE which gets automatically generated by the asm-offsets tool. In the result, all definitions of this value can be deleted from the board config files. We have to make sure that all files that reference such data include the new <asm-offsets.h> file. No other changes have been done yet, but it is obvious that similar changes / simplifications can be done for other, related macro definitions as well. Signed-off-by: Wolfgang Denk <wd@denx.de> Acked-by: Kumar Gala <galak@kernel.crashing.org>
405 lines
12 KiB
C
405 lines
12 KiB
C
/*
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* Copyright (c) 2005 Freescale Semiconductor, Inc.
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*
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* (C) Copyright 2006
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* Alex Bounine , Tundra Semiconductor Corp.
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* Roy Zang , <tie-fei.zang@freescale.com> Freescale Corp.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* board specific configuration options for Freescale
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* MPC7448HPC2 (High-Performance Computing II) (Taiga) board
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*
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/* Board Configuration Definitions */
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/* MPC7448HPC2 (High-Performance Computing II) (Taiga) board */
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#define CONFIG_MPC7448HPC2
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#define CONFIG_74xx
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#define CONFIG_HIGH_BATS /* High BATs supported */
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#define CONFIG_ALTIVEC /* undef to disable */
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#define CONFIG_SYS_TEXT_BASE 0xFF000000
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#define CONFIG_SYS_BOARD_NAME "MPC7448 HPC II"
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#define CONFIG_IDENT_STRING " Freescale MPC7448 HPC II"
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#define CONFIG_SYS_OCN_CLK 133000000 /* 133 MHz */
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#define CONFIG_SYS_BUS_CLK 133000000
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#define CONFIG_SYS_CLK_SPREAD /* Enable Spread-Spectrum Clock generation */
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#undef CONFIG_ECC /* disable ECC support */
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/* Board-specific Initialization Functions to be called */
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#define CONFIG_SYS_BOARD_ASM_INIT
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#define CONFIG_BOARD_EARLY_INIT_F
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#define CONFIG_BOARD_EARLY_INIT_R
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#define CONFIG_MISC_INIT_R
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#define CONFIG_HAS_ETH0
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#define CONFIG_HAS_ETH1
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#define CONFIG_ENV_OVERWRITE
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_BAUDRATE 115200 /* console baudrate = 115000 */
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/*#define CONFIG_SYS_HUSH_PARSER */
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#undef CONFIG_SYS_HUSH_PARSER
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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/* Pass open firmware flat tree */
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#define CONFIG_OF_LIBFDT 1
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#define CONFIG_OF_BOARD_SETUP 1
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#define OF_TSI "tsi108@c0000000"
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#define OF_TBCLK (bd->bi_busfreq / 8)
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#define OF_STDOUT_PATH "/tsi108@c0000000/serial@7808"
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/*
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* The following defines let you select what serial you want to use
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* for your console driver.
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*
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* what to do:
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* If you have hacked a serial cable onto the second DUART channel,
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* change the CONFIG_SYS_DUART port from 1 to 0 below.
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*
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*/
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_OCN_CLK * 8
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_TSI108_CSR_RST_BASE+0x7808)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_TSI108_CSR_RST_BASE+0x7C08)
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
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#define CONFIG_ZERO_BOOTDELAY_CHECK
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#undef CONFIG_BOOTARGS
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/* #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" */
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#if (CONFIG_BOOTDELAY >= 0)
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#define CONFIG_BOOTCOMMAND "tftpboot 0x400000 zImage.initrd.elf;\
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setenv bootargs $(bootargs) $(bootargs_root) nfsroot=$(serverip):$(rootpath) \
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ip=$(ipaddr):$(serverip)$(bootargs_end); bootm 0x400000; "
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#define CONFIG_BOOTARGS "console=ttyS0,115200"
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#endif
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#undef CONFIG_EXTRA_ENV_SETTINGS
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#define CONFIG_SERIAL "No. 1"
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/* Networking Configuration */
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#define CONFIG_TSI108_ETH
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#define CONFIG_TSI108_ETH_NUM_PORTS 2
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#define CONFIG_NET_MULTI
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#define CONFIG_BOOTFILE zImage.initrd.elf
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#define CONFIG_LOADADDR 0x400000
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/*-------------------------------------------------------------------------- */
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#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
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#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_SUBNETMASK
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_BOOTFILESIZE
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_ASKENV
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#define CONFIG_CMD_CACHE
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_SDRAM
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#define CONFIG_CMD_EEPROM
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#define CONFIG_CMD_FLASH
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#define CONFIG_CMD_SAVEENV
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#define CONFIG_CMD_BSP
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_DATE
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/*set date in u-boot*/
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#define CONFIG_RTC_M48T35A
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#define CONFIG_SYS_NVRAM_BASE_ADDR 0xfc000000
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#define CONFIG_SYS_NVRAM_SIZE 0x8000
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_VERSION_VARIABLE 1
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#define CONFIG_TSI108_I2C
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#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C EEPROM page 1 */
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
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#else
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)/* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */
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#define CONFIG_SYS_LOAD_ADDR 0x00400000 /* default load address */
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#define CONFIG_SYS_HZ 1000 /* decr freq: 1ms ticks */
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/*
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* Low Level Configuration Settings
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* (address mappings, register initial values, etc.)
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* You should know what you are doing if you make changes here.
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*/
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area
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*/
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/*
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* When locking data in cache you should point the CONFIG_SYS_INIT_RAM_ADDRESS
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* To an unused memory region. The stack will remain in cache until RAM
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* is initialized
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*/
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#undef CONFIG_SYS_INIT_RAM_LOCK
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#define CONFIG_SYS_INIT_RAM_ADDR 0x07d00000 /* unused memory region */
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#define CONFIG_SYS_INIT_RAM_SIZE 0x4000/* larger space - we have SDRAM initialized */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
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*/
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#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* first 256 MB of SDRAM */
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#define CONFIG_SYS_SDRAM1_BASE 0x10000000 /* next 256MB of SDRAM */
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#define CONFIG_SYS_SDRAM2_BASE 0x40000000 /* beginning of non-cacheable alias for SDRAM - first 256MB */
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#define CONFIG_SYS_SDRAM3_BASE 0x50000000 /* next Non-Cacheable 256MB of SDRAM */
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#define CONFIG_SYS_PCI_PFM_BASE 0x80000000 /* Prefetchable (cacheable) PCI/X PFM and SDRAM OCN (128MB+128MB) */
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#define CONFIG_SYS_PCI_MEM32_BASE 0xE0000000 /* Non-Cacheable PCI/X MEM and SDRAM OCN (128MB+128MB) */
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#define CONFIG_SYS_MISC_REGION_BASE 0xf0000000 /* Base Address for (PCI/X + Flash) region */
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#define CONFIG_SYS_FLASH_BASE 0xff000000 /* Base Address of Flash device */
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#define CONFIG_SYS_FLASH_BASE2 0xfe000000 /* Alternate Flash Base Address */
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#define CONFIG_VERY_BIG_RAM /* we will use up to 256M memory for cause we are short of BATS */
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#define PCI0_IO_BASE_BOOTM 0xfd000000
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#define CONFIG_SYS_RESET_ADDRESS 0x3fffff00
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#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* u-boot code base */
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#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */
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/* Peripheral Device section */
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/*
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* Resources on the Tsi108
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*/
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#define CONFIG_SYS_TSI108_CSR_RST_BASE 0xC0000000 /* Tsi108 CSR base after reset */
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#define CONFIG_SYS_TSI108_CSR_BASE CONFIG_SYS_TSI108_CSR_RST_BASE /* Runtime Tsi108 CSR base */
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#define ENABLE_PCI_CSR_BAR /* enables access to Tsi108 CSRs from the PCI/X bus */
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#undef DISABLE_PBM
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/*
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* PCI stuff
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*
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*/
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#define CONFIG_PCI /* include pci support */
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#define CONFIG_TSI108_PCI /* include tsi108 pci support */
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#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
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#define PCI_HOST_FORCE 1 /* configure as pci host */
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#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
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#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
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#define CONFIG_PCI_PNP /* do pci plug-and-play */
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/* PCI MEMORY MAP section */
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/* PCI view of System Memory */
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#define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000
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#define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000
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#define CONFIG_SYS_PCI_MEMORY_SIZE 0x80000000
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/* PCI Memory Space */
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#define CONFIG_SYS_PCI_MEM_BUS (CONFIG_SYS_PCI_MEM_PHYS)
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#define CONFIG_SYS_PCI_MEM_PHYS (CONFIG_SYS_PCI_MEM32_BASE) /* 0xE0000000 */
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#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256 MB space for PCI/X Mem + SDRAM OCN */
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/* PCI I/O Space */
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#define CONFIG_SYS_PCI_IO_BUS 0x00000000
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#define CONFIG_SYS_PCI_IO_PHYS 0xfa000000 /* Changed from fd000000 */
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#define CONFIG_SYS_PCI_IO_SIZE 0x01000000 /* 16MB */
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/* PCI Config Space mapping */
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#define CONFIG_SYS_PCI_CFG_BASE 0xfb000000 /* Changed from FE000000 */
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#define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 /* 16MB */
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#define CONFIG_SYS_IBAT0U 0xFE0003FF
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#define CONFIG_SYS_IBAT0L 0xFE000002
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#define CONFIG_SYS_IBAT1U 0x00007FFF
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#define CONFIG_SYS_IBAT1L 0x00000012
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#define CONFIG_SYS_IBAT2U 0x80007FFF
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#define CONFIG_SYS_IBAT2L 0x80000022
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#define CONFIG_SYS_IBAT3U 0x00000000
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#define CONFIG_SYS_IBAT3L 0x00000000
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#define CONFIG_SYS_IBAT4U 0x00000000
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#define CONFIG_SYS_IBAT4L 0x00000000
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#define CONFIG_SYS_IBAT5U 0x00000000
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#define CONFIG_SYS_IBAT5L 0x00000000
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#define CONFIG_SYS_IBAT6U 0x00000000
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#define CONFIG_SYS_IBAT6L 0x00000000
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#define CONFIG_SYS_IBAT7U 0x00000000
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#define CONFIG_SYS_IBAT7L 0x00000000
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#define CONFIG_SYS_DBAT0U 0xE0003FFF
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#define CONFIG_SYS_DBAT0L 0xE000002A
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#define CONFIG_SYS_DBAT1U 0x00007FFF
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#define CONFIG_SYS_DBAT1L 0x00000012
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#define CONFIG_SYS_DBAT2U 0x00000000
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#define CONFIG_SYS_DBAT2L 0x00000000
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#define CONFIG_SYS_DBAT3U 0xC0000003
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#define CONFIG_SYS_DBAT3L 0xC000002A
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#define CONFIG_SYS_DBAT4U 0x00000000
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#define CONFIG_SYS_DBAT4L 0x00000000
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#define CONFIG_SYS_DBAT5U 0x00000000
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#define CONFIG_SYS_DBAT5L 0x00000000
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#define CONFIG_SYS_DBAT6U 0x00000000
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#define CONFIG_SYS_DBAT6L 0x00000000
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#define CONFIG_SYS_DBAT7U 0x00000000
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#define CONFIG_SYS_DBAT7L 0x00000000
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/* I2C addresses for the two DIMM SPD chips */
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#define DIMM0_I2C_ADDR 0x51
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#define DIMM1_I2C_ADDR 0x52
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Flash can be at one of two addresses */
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#define FLASH_BANK_SIZE 0x01000000 /* 16 MB Total */
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#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, /* CONFIG_SYS_FLASH_BASE2 */ }
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_SYS_WRITE_SWAPPED_DATA
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#define PHYS_FLASH_SIZE 0x01000000
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#define CONFIG_SYS_MAX_FLASH_SECT (128)
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#define CONFIG_ENV_IS_IN_NVRAM
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#define CONFIG_ENV_ADDR 0xFC000000
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#define CONFIG_ENV_OFFSET 0x00000000 /* Offset of Environment Sector */
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#define CONFIG_ENV_SIZE 0x00000400 /* Total Size of Environment Space */
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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#endif
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/*-----------------------------------------------------------------------
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* L2CR setup -- make sure this is right for your board!
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* look in include/mpc74xx.h for the defines used here
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*/
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#undef CONFIG_SYS_L2
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#define L2_INIT 0
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#define L2_ENABLE (L2_INIT | L2CR_L2E)
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#define CONFIG_SYS_SERIAL_HANG_IN_EXCEPTION
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#endif /* __CONFIG_H */
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