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https://github.com/brain-hackers/u-boot-brain
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25ddd1fb0a
CONFIG_SYS_GBL_DATA_SIZE has always been just a bad workarond for not being able to use "sizeof(struct global_data)" in assembler files. Recent experience has shown that manual synchronization is not reliable enough. This patch renames CONFIG_SYS_GBL_DATA_SIZE into GENERATED_GBL_DATA_SIZE which gets automatically generated by the asm-offsets tool. In the result, all definitions of this value can be deleted from the board config files. We have to make sure that all files that reference such data include the new <asm-offsets.h> file. No other changes have been done yet, but it is obvious that similar changes / simplifications can be done for other, related macro definitions as well. Signed-off-by: Wolfgang Denk <wd@denx.de> Acked-by: Kumar Gala <galak@kernel.crashing.org>
384 lines
13 KiB
C
384 lines
13 KiB
C
/*
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* (C) Copyright 2001, 2002
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include <mpc8xx_irq.h>
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# ifdef DEBUG
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# warning DEBUG Defined
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# endif /* DEBUG */
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_MPC860 1
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#define CONFIG_IAD210 1 /* ...on a IAD210 module */
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#define CONFIG_MPC860T 1
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#define CONFIG_MPC862 1
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#define CONFIG_SYS_TEXT_BASE 0x08000000
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#undef CONFIG_8xx_CONS_SMC1
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#undef CONFIG_8xx_CONS_SMC2
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#define CONFIG_8xx_CONS_SCC2 /* V24 on SCC2 */
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#undef CONFIG_8xx_CONS_NONE
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#define CONFIG_BAUDRATE 9600
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# define MPC8XX_FACT 16
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# define CONFIG_8xx_GCLK_FREQ (64000000L) /* define if can't use get_gclk_freq */
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# define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
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#if 0
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# define CONFIG_BOOTDELAY -1 /* autoboot disabled */
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#else
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# define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#endif
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#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
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/* using this define saves us updating another source file */
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#define CONFIG_BOARD_EARLY_INIT_F 1
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#define CONFIG_MISC_INIT_R
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#undef CONFIG_BOOTARGS
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/* #define CONFIG_BOOTCOMMAND \
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"bootp;" \
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"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
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"bootm"
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*/
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#define CONFIG_BOOTCOMMAND \
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"setenv bootargs root=/dev/nfs" \
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"ip=192.168.28.129:139.10.137.138:192.168.28.1:255.255.255.0:iadlinux002::off; " \
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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/* #define CONFIG_STATUS_LED 1*/ /* Status LED enabled */
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_SUBNETMASK
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_BOOTFILESIZE
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# undef CONFIG_SCC1_ENET /* disable SCC1 ethernet */
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# define CONFIG_FEC_ENET 1 /* use FEC ethernet */
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# define CONFIG_MII 1
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# define CONFIG_SYS_DISCOVER_PHY 1
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# define CONFIG_FEC_UTOPIA 1
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# define CONFIG_ETHADDR 08:00:06:26:A2:6D
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# define CONFIG_IPADDR 192.168.28.128
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# define CONFIG_SERVERIP 139.10.137.138
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# define CONFIG_SYS_DISCOVER_PHY 1
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#define CONFIG_MAC_PARTITION
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#define CONFIG_DOS_PARTITION
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/* enable I2C and select the hardware/software driver */
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#undef CONFIG_HARD_I2C /* I2C with hardware support */
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#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
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# define CONFIG_SYS_I2C_SPEED 50000
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# define CONFIG_SYS_I2C_SLAVE 0xDD
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# define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
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/*
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* Software (bit-bang) I2C driver configuration
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*/
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#define PB_SCL 0x00000020 /* PB 26 */
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#define PB_SDA 0x00000010 /* PB 27 */
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#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
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#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
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#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
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#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
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#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
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else immr->im_cpm.cp_pbdat &= ~PB_SDA
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#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
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else immr->im_cpm.cp_pbdat &= ~PB_SCL
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#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
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#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_ASKENV
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_DATE
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */
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#define CONFIG_SYS_LOAD_ADDR 0x00100000
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#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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/*
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* Low Level Configuration Settings
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* (address mappings, register initial values, etc.)
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* You should know what you are doing if you make changes here.
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*/
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/*-----------------------------------------------------------------------
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* Internal Memory Mapped Register
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*/
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#define CONFIG_SYS_IMMR 0xFFF00000
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#define CONFIG_SYS_IMMR_SIZE ((uint)(64 * 1024))
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in DPRAM)
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*/
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#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
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#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
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*/
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_FLASH_BASE 0x08000000
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#define CONFIG_SYS_FLASH_SIZE ((uint)(4 * 1024 * 1024)) /* max 16Mbyte */
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#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
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#if defined(DEBUG)
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# define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
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#else
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# define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
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#endif
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# define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
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# define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
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#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_OFFSET 0x8000
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#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
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#endif
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/*-----------------------------------------------------------------------
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* SYPCR - System Protection Control 11-9
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* SYPCR can only be written once after reset!
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*-----------------------------------------------------------------------
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* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
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*/
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#if defined(CONFIG_WATCHDOG)
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#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
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SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
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#else
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#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
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#endif
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/*-----------------------------------------------------------------------
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* SIUMCR - SIU Module Configuration 11-6
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*-----------------------------------------------------------------------
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* PCMCIA config., multi-function pin tri-state
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*/
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#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
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/*-----------------------------------------------------------------------
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* TBSCR - Time Base Status and Control 11-26
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*-----------------------------------------------------------------------
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* Clear Reference Interrupt Status, Timebase freezing enabled
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*/
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#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
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/*-----------------------------------------------------------------------
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* PISCR - Periodic Interrupt Status and Control 11-31
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*-----------------------------------------------------------------------
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* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
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*/
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#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
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/*-----------------------------------------------------------------------
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* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
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*-----------------------------------------------------------------------
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* set the PLL, the low-power modes and the reset control (15-29)
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*/
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#define CONFIG_SYS_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
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PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
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/*-----------------------------------------------------------------------
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* SCCR - System Clock and reset Control Register 15-27
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*-----------------------------------------------------------------------
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* Set clock output, timebase and RTC source and divider,
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* power management and some other internal clocks
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*/
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#define SCCR_MASK SCCR_EBDF11
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#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_COM00 | SCCR_DFSYNC00 | \
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SCCR_DFBRG00 | SCCR_DFNL000 | SCCR_DFNH000 | \
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SCCR_DFLCD000 |SCCR_DFALCD00 )
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/*-----------------------------------------------------------------------
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* RCCR - RISC Controller Configuration Register 19-4
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*-----------------------------------------------------------------------
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*/
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/* +0x09C4 => DRQP = 10 (IDMA requests have lowest priority) */
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#define CONFIG_SYS_RCCR 0x0020
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/*-----------------------------------------------------------------------
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* PCMCIA stuff
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*-----------------------------------------------------------------------
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*/
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#define PCMCIA_MEM_ADDR ((uint)0xff020000)
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#define PCMCIA_MEM_SIZE ((uint)(64 * 1024))
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/*-----------------------------------------------------------------------
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*
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*-----------------------------------------------------------------------
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*
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*/
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#define CONFIG_SYS_DER 0
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/* Because of the way the 860 starts up and assigns CS0 the
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* entire address space, we have to set the memory controller
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* differently. Normally, you write the option register
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* first, and then enable the chip select by writing the
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* base register. For CS0, you must write the base register
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* first, followed by the option register.
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*/
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/*
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* Init Memory Controller:
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*
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* BR0 and OR0 (FLASH)
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*/
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#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */
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/* used to re-map FLASH both when starting from SRAM or FLASH:
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* restrict access enough to keep SRAM working (if any)
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* but not too much to meddle with FLASH accesses
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*/
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#define CONFIG_SYS_REMAP_OR_AM 0xF8000000 /* OR addr mask */
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#define CONFIG_SYS_PRELIM_OR_AM 0xF8000000 /* OR addr mask */
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/* FLASH timing:
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TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */
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#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | \
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OR_SCY_3_CLK | OR_EHTR)
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#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
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#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
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/*
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* BR2/3 and OR2/3 (SDRAM)
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*
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*/
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#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM bank #0 */
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#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
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/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
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#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | OR_CSNT_SAM | OR_BI | OR_ACS_DIV4)
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#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
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#define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V)
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/*
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* Memory Periodic Timer Prescaler
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*/
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/* periodic timer for refresh */
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#define CONFIG_SYS_MAMR_PTA 124 /* start with divider for 64 MHz */
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/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
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#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV32 /* setting for 1 bank */
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/*
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* MAMR settings for SDRAM
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*/
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#define CONFIG_SYS_MAMR ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
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MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
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MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_8X)
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#ifdef CONFIG_MPC860T
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/* Interrupt level assignments.
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*/
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#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */
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#endif /* CONFIG_MPC860T */
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#endif /* __CONFIG_H */
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