mirror of
https://github.com/brain-hackers/u-boot-brain
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![Shengzhou Liu](/assets/img/avatar_default.png)
T1024RDB is a Freescale Reference Design Board that hosts the T1024 SoC. T1024RDB board Overview ----------------------- - T1024 SoC integrating two 64-bit e5500 cores up to 1.4GHz - CoreNet fabric supporting coherent and noncoherent transactions with prioritization and bandwidth allocation - 32-/64-bit DDR3L SDRAM memory controller with ECC and interleaving support - Accelerator: DPAA components consist of FMan, BMan, QMan, DCE and SEC - Ethernet interfaces: - Two 10M/100M/1G RGMII ports on-board - one 10Gbps XFI interface - PCIe: Three PCIe controllers: one PCIe Slot and two Mini-PCIe connectors. - SerDes: 4 lanes up to 10.3125GHz - IFC: 128MB NOR Flash, 512MB NAND Flash and CPLD - eSPI: 64MB N25Q512 SPI flash. - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB) - USB: Two Type-A USB2.0 ports with internal PHY - eSDHC: Support SD, SDHC, SDXC and MMC/eMMC - I2C: Four I2C controllers - UART: Two UART serial ports Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> [York Sun: Fix ft_board_setup() type, fix MAINTAINERS for SECURE_BOOT Fix Kconfig by adding SUPPORT_SPL] Reviewed-by: York Sun <yorksun@freescale.com>
27 lines
496 B
INI
27 lines
496 B
INI
#PBI commands
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#Initialize CPC1
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09010000 00200400
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09138000 00000000
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091380c0 00000100
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#Configure CPC1 as 256KB SRAM
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09010100 00000000
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09010104 fffc0007
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09010f00 08000000
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09010000 80000000
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#Configure LAW for CPC1
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09000cd0 00000000
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09000cd4 fffc0000
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09000cd8 81000011
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#Configure alternate space
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09000010 00000000
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09000014 ff000000
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09000018 81000000
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#Configure SPI controller
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09110000 80000403
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09110020 2d170008
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09110024 00100008
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09110028 00100008
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0911002c 00100008
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#Flush PBL data
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091380c0 000FFFFF
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