mirror of
https://github.com/brain-hackers/u-boot-brain
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6bd8231a6d
As the Ocelots SoCs, this family of SoCs are found in the Microsemi Switches solution. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
63 lines
1.7 KiB
ArmAsm
63 lines
1.7 KiB
ArmAsm
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2018 Microsemi Corporation
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*/
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#include <asm/asm.h>
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#include <asm/regdef.h>
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#define BASE_MACRO 0x600a0000
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#define REG_OFFSET(t, o) (t + (o*4))
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#define REG_MACRO(x) REG_OFFSET(BASE_MACRO, x)
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#define BIT(nr) (1 << (nr))
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#define MACRO_CTRL_PLL5G_STATUS_PLL5G_STATUS0 REG_MACRO(6)
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#define MACRO_CTRL_PLL5G_STATUS_PLL5G_STATUS0_LOCK_STATUS BIT(0)
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#define MACRO_CTRL_PLL5G_CFG_PLL5G_CFG2 REG_MACRO(2)
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#define MACRO_CTRL_PLL5G_CFG_PLL5G_CFG0 REG_MACRO(0)
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#define MACRO_CTRL_PLL5G_CFG_PLL5G_CFG0_CPU_CLK_DIV (0x3F << 6)
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#define MACRO_CTRL_PLL5G_CFG_PLL5G_CFG0_CPU_CLK_DIV_ENC(x) (x << 6)
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.set noreorder
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LEAF(pll_init)
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/* Make sure PLL is locked */
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lw v0, MACRO_CTRL_PLL5G_STATUS_PLL5G_STATUS0
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andi v1, v0, MACRO_CTRL_PLL5G_STATUS_PLL5G_STATUS0_LOCK_STATUS
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bne v1, zero, 1f
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nop
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/* Black magic from frontend */
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li v1, 0x00610400
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sw v1, MACRO_CTRL_PLL5G_CFG_PLL5G_CFG2
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li v1, 0x00610c00
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sw v1, MACRO_CTRL_PLL5G_CFG_PLL5G_CFG2
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li v1, 0x00610800
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sw v1, MACRO_CTRL_PLL5G_CFG_PLL5G_CFG2
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li v1, 0x00610000
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sw v1, MACRO_CTRL_PLL5G_CFG_PLL5G_CFG2
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/* Wait for lock */
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2: lw v0, MACRO_CTRL_PLL5G_STATUS_PLL5G_STATUS0
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andi v1, v0, MACRO_CTRL_PLL5G_STATUS_PLL5G_STATUS0_LOCK_STATUS
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/* Keep looping if zero (no lock bit yet) */
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beq v1, zero, 2b
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nop
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/* Setup PLL CPU clock divider for 416MHz */
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1: lw v0, MACRO_CTRL_PLL5G_CFG_PLL5G_CFG0
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/* Keep reserved bits */
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li v1, ~MACRO_CTRL_PLL5G_CFG_PLL5G_CFG0_CPU_CLK_DIV
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and v0, v0, v1
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/* Set code 6 ~ 416.66 MHz */
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ori v0, v0, MACRO_CTRL_PLL5G_CFG_PLL5G_CFG0_CPU_CLK_DIV_ENC(6)
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sw v0, MACRO_CTRL_PLL5G_CFG_PLL5G_CFG0
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jr ra
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nop
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END(pll_init)
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