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https://github.com/brain-hackers/u-boot-brain
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7048bb13b2
This patch fixes an stability issue seen on some vcoreiii targets, which was root caused to a cache inconsistency situation. The inconsistency was caused by having kuseg pointing to NOR area but used as a stack/gd/heap area during initialization, while only relatively late remapping the RAM area into kuseg position. The fix is to initialize the DDR right after the TLB setup, and then remapping it into position before gd/stack/heap usage. Reported-by: Ramin Seyed-Moussavi <ramin.moussavi@yacoub.de> Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Reviewed-by: Horatiu Vultur <horatiu.vultur@microchip.com> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
46 lines
817 B
ArmAsm
46 lines
817 B
ArmAsm
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2018 Microsemi Corporation
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*/
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#include <asm/asm.h>
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#include <asm/regdef.h>
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.set noreorder
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.extern vcoreiii_tlb_init
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.extern vcoreiii_ddr_init
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#ifdef CONFIG_SOC_LUTON
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.extern pll_init
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#endif
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LEAF(lowlevel_init)
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/*
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* As we have no stack yet, we can assume the restricted
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* luxury of the sX-registers without saving them
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*/
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/* Modify ra/s0 such we return to physical NOR location */
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li t0, 0x0fffffff
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li t1, CONFIG_SYS_TEXT_BASE
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and s0, ra, t0
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add s0, s0, t1
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jal vcoreiii_tlb_init
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nop
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#ifdef CONFIG_SOC_LUTON
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jal pll_init
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nop
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#endif
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/* Initialize DDR controller to enable stack/gd/heap */
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0:
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jal vcoreiii_ddr_init
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nop
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bnez v0, 0b /* Retry on error */
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nop
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jr s0
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nop
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END(lowlevel_init)
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