mirror of
https://github.com/brain-hackers/u-boot-brain
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caa4daa2ae
We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
159 lines
3.6 KiB
C
159 lines
3.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
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*
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* Generic reset driver for x86 processor
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*/
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#include <common.h>
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#include <dm.h>
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#include <efi_loader.h>
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#include <pch.h>
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#include <sysreset.h>
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#include <acpi/acpi_s3.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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struct x86_sysreset_platdata {
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struct udevice *pch;
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};
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/*
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* Power down the machine by using the power management sleep control
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* of the chipset. This will currently only work on Intel chipsets.
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* However, adapting it to new chipsets is fairly simple. You will
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* have to find the IO address of the power management register block
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* in your southbridge, and look up the appropriate SLP_TYP_S5 value
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* from your southbridge's data sheet.
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*
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* This function never returns.
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*/
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int pch_sysreset_power_off(struct udevice *dev)
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{
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struct x86_sysreset_platdata *plat = dev_get_platdata(dev);
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struct pch_pmbase_info pm;
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u32 reg32;
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int ret;
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if (!plat->pch)
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return -ENOENT;
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ret = pch_ioctl(plat->pch, PCH_REQ_PMBASE_INFO, &pm, sizeof(pm));
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if (ret)
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return ret;
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/*
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* Mask interrupts or system might stay in a coma, not executing code
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* anymore, but not powered off either.
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*/
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asm("cli");
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/*
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* Avoid any GPI waking the system from S5* or the system might stay in
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* a coma
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*/
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outl(0x00000000, pm.base + pm.gpio0_en_ofs);
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/* Clear Power Button Status */
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outw(PWRBTN_STS, pm.base + pm.pm1_sts_ofs);
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/* PMBASE + 4, Bit 10-12, Sleeping Type, * set to 111 -> S5, soft_off */
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reg32 = inl(pm.base + pm.pm1_cnt_ofs);
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/* Set Sleeping Type to S5 (poweroff) */
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reg32 &= ~(SLP_EN | SLP_TYP);
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reg32 |= SLP_TYP_S5;
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outl(reg32, pm.base + pm.pm1_cnt_ofs);
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/* Now set the Sleep Enable bit */
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reg32 |= SLP_EN;
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outl(reg32, pm.base + pm.pm1_cnt_ofs);
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for (;;)
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asm("hlt");
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}
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static int x86_sysreset_request(struct udevice *dev, enum sysreset_t type)
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{
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int value;
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int ret;
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switch (type) {
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case SYSRESET_WARM:
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value = SYS_RST | RST_CPU;
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break;
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case SYSRESET_COLD:
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value = SYS_RST | RST_CPU | FULL_RST;
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break;
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case SYSRESET_POWER_OFF:
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ret = pch_sysreset_power_off(dev);
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if (ret)
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return ret;
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return -EINPROGRESS;
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default:
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return -ENOSYS;
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}
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outb(value, IO_PORT_RESET);
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return -EINPROGRESS;
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}
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static int x86_sysreset_get_last(struct udevice *dev)
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{
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return SYSRESET_POWER;
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}
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#ifdef CONFIG_EFI_LOADER
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void __efi_runtime EFIAPI efi_reset_system(
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enum efi_reset_type reset_type,
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efi_status_t reset_status,
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unsigned long data_size, void *reset_data)
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{
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int value;
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/*
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* inline this code since we are not caused in the context of a
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* udevice and passing NULL to x86_sysreset_request() is too horrible.
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*/
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if (reset_type == EFI_RESET_COLD ||
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reset_type == EFI_RESET_PLATFORM_SPECIFIC)
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value = SYS_RST | RST_CPU | FULL_RST;
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else /* assume EFI_RESET_WARM since we cannot return an error */
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value = SYS_RST | RST_CPU;
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outb(value, IO_PORT_RESET);
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/* TODO EFI_RESET_SHUTDOWN */
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while (1) { }
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}
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#endif
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static int x86_sysreset_probe(struct udevice *dev)
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{
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struct x86_sysreset_platdata *plat = dev_get_platdata(dev);
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/* Locate the PCH if there is one. It isn't essential */
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uclass_first_device(UCLASS_PCH, &plat->pch);
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return 0;
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}
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static const struct udevice_id x86_sysreset_ids[] = {
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{ .compatible = "x86,reset" },
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{ }
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};
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static struct sysreset_ops x86_sysreset_ops = {
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.request = x86_sysreset_request,
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.get_last = x86_sysreset_get_last,
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};
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U_BOOT_DRIVER(x86_reset) = {
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.name = "x86_reset",
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.id = UCLASS_SYSRESET,
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.of_match = x86_sysreset_ids,
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.ops = &x86_sysreset_ops,
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.probe = x86_sysreset_probe,
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.plat_auto = sizeof(struct x86_sysreset_platdata),
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};
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