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https://github.com/brain-hackers/u-boot-brain
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41575d8e4c
This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
436 lines
11 KiB
C
436 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2019 BayLibre, SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*/
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#include <common.h>
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#include <dm.h>
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#include <log.h>
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#include <malloc.h>
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#include <power-domain-uclass.h>
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#include <regmap.h>
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#include <syscon.h>
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#include <reset.h>
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#include <clk.h>
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#include <dt-bindings/power/meson-g12a-power.h>
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#include <dt-bindings/power/meson-sm1-power.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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/* AO Offsets */
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#define AO_RTI_GEN_PWR_SLEEP0 (0x3a << 2)
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#define AO_RTI_GEN_PWR_ISO0 (0x3b << 2)
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/* HHI Offsets */
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#define HHI_MEM_PD_REG0 (0x40 << 2)
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#define HHI_VPU_MEM_PD_REG0 (0x41 << 2)
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#define HHI_VPU_MEM_PD_REG1 (0x42 << 2)
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#define HHI_VPU_MEM_PD_REG3 (0x43 << 2)
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#define HHI_VPU_MEM_PD_REG4 (0x44 << 2)
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#define HHI_AUDIO_MEM_PD_REG0 (0x45 << 2)
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#define HHI_NANOQ_MEM_PD_REG0 (0x46 << 2)
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#define HHI_NANOQ_MEM_PD_REG1 (0x47 << 2)
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#define HHI_VPU_MEM_PD_REG2 (0x4d << 2)
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struct meson_ee_pwrc;
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struct meson_ee_pwrc_domain;
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struct meson_ee_pwrc_mem_domain {
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unsigned int reg;
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unsigned int mask;
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};
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struct meson_ee_pwrc_top_domain {
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unsigned int sleep_reg;
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unsigned int sleep_mask;
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unsigned int iso_reg;
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unsigned int iso_mask;
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};
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struct meson_ee_pwrc_domain_desc {
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char *name;
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unsigned int reset_names_count;
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unsigned int clk_names_count;
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struct meson_ee_pwrc_top_domain *top_pd;
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unsigned int mem_pd_count;
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struct meson_ee_pwrc_mem_domain *mem_pd;
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bool (*get_power)(struct power_domain *power_domain);
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};
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struct meson_ee_pwrc_domain_data {
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unsigned int count;
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struct meson_ee_pwrc_domain_desc *domains;
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};
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/* TOP Power Domains */
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static struct meson_ee_pwrc_top_domain g12a_pwrc_vpu = {
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.sleep_reg = AO_RTI_GEN_PWR_SLEEP0,
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.sleep_mask = BIT(8),
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.iso_reg = AO_RTI_GEN_PWR_SLEEP0,
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.iso_mask = BIT(9),
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};
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#define SM1_EE_PD(__bit) \
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{ \
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.sleep_reg = AO_RTI_GEN_PWR_SLEEP0, \
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.sleep_mask = BIT(__bit), \
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.iso_reg = AO_RTI_GEN_PWR_ISO0, \
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.iso_mask = BIT(__bit), \
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}
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static struct meson_ee_pwrc_top_domain sm1_pwrc_vpu = SM1_EE_PD(8);
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static struct meson_ee_pwrc_top_domain sm1_pwrc_nna = SM1_EE_PD(16);
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static struct meson_ee_pwrc_top_domain sm1_pwrc_usb = SM1_EE_PD(17);
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static struct meson_ee_pwrc_top_domain sm1_pwrc_pci = SM1_EE_PD(18);
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static struct meson_ee_pwrc_top_domain sm1_pwrc_ge2d = SM1_EE_PD(19);
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/* Memory PD Domains */
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#define VPU_MEMPD(__reg) \
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{ __reg, GENMASK(1, 0) }, \
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{ __reg, GENMASK(3, 2) }, \
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{ __reg, GENMASK(5, 4) }, \
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{ __reg, GENMASK(7, 6) }, \
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{ __reg, GENMASK(9, 8) }, \
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{ __reg, GENMASK(11, 10) }, \
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{ __reg, GENMASK(13, 12) }, \
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{ __reg, GENMASK(15, 14) }, \
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{ __reg, GENMASK(17, 16) }, \
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{ __reg, GENMASK(19, 18) }, \
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{ __reg, GENMASK(21, 20) }, \
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{ __reg, GENMASK(23, 22) }, \
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{ __reg, GENMASK(25, 24) }, \
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{ __reg, GENMASK(27, 26) }, \
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{ __reg, GENMASK(29, 28) }, \
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{ __reg, GENMASK(31, 30) }
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#define VPU_HHI_MEMPD(__reg) \
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{ __reg, BIT(8) }, \
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{ __reg, BIT(9) }, \
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{ __reg, BIT(10) }, \
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{ __reg, BIT(11) }, \
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{ __reg, BIT(12) }, \
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{ __reg, BIT(13) }, \
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{ __reg, BIT(14) }, \
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{ __reg, BIT(15) }
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static struct meson_ee_pwrc_mem_domain g12a_pwrc_mem_vpu[] = {
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VPU_MEMPD(HHI_VPU_MEM_PD_REG0),
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VPU_MEMPD(HHI_VPU_MEM_PD_REG1),
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VPU_MEMPD(HHI_VPU_MEM_PD_REG2),
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VPU_HHI_MEMPD(HHI_MEM_PD_REG0),
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};
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static struct meson_ee_pwrc_mem_domain g12a_pwrc_mem_eth[] = {
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{ HHI_MEM_PD_REG0, GENMASK(3, 2) },
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};
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static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_vpu[] = {
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VPU_MEMPD(HHI_VPU_MEM_PD_REG0),
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VPU_MEMPD(HHI_VPU_MEM_PD_REG1),
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VPU_MEMPD(HHI_VPU_MEM_PD_REG2),
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VPU_MEMPD(HHI_VPU_MEM_PD_REG3),
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{ HHI_VPU_MEM_PD_REG4, GENMASK(1, 0) },
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{ HHI_VPU_MEM_PD_REG4, GENMASK(3, 2) },
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{ HHI_VPU_MEM_PD_REG4, GENMASK(5, 4) },
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{ HHI_VPU_MEM_PD_REG4, GENMASK(7, 6) },
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VPU_HHI_MEMPD(HHI_MEM_PD_REG0),
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};
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static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_nna[] = {
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{ HHI_NANOQ_MEM_PD_REG0, 0xff },
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{ HHI_NANOQ_MEM_PD_REG1, 0xff },
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};
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static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_usb[] = {
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{ HHI_MEM_PD_REG0, GENMASK(31, 30) },
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};
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static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_pcie[] = {
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{ HHI_MEM_PD_REG0, GENMASK(29, 26) },
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};
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static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_ge2d[] = {
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{ HHI_MEM_PD_REG0, GENMASK(25, 18) },
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};
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static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_audio[] = {
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{ HHI_MEM_PD_REG0, GENMASK(5, 4) },
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{ HHI_AUDIO_MEM_PD_REG0, GENMASK(1, 0) },
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{ HHI_AUDIO_MEM_PD_REG0, GENMASK(3, 2) },
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{ HHI_AUDIO_MEM_PD_REG0, GENMASK(5, 4) },
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{ HHI_AUDIO_MEM_PD_REG0, GENMASK(7, 6) },
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{ HHI_AUDIO_MEM_PD_REG0, GENMASK(13, 12) },
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{ HHI_AUDIO_MEM_PD_REG0, GENMASK(15, 14) },
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{ HHI_AUDIO_MEM_PD_REG0, GENMASK(17, 16) },
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{ HHI_AUDIO_MEM_PD_REG0, GENMASK(19, 18) },
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{ HHI_AUDIO_MEM_PD_REG0, GENMASK(21, 20) },
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{ HHI_AUDIO_MEM_PD_REG0, GENMASK(23, 22) },
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{ HHI_AUDIO_MEM_PD_REG0, GENMASK(25, 24) },
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{ HHI_AUDIO_MEM_PD_REG0, GENMASK(27, 26) },
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};
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#define VPU_PD(__name, __top_pd, __mem, __get_power, __resets, __clks) \
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{ \
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.name = __name, \
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.reset_names_count = __resets, \
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.clk_names_count = __clks, \
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.top_pd = __top_pd, \
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.mem_pd_count = ARRAY_SIZE(__mem), \
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.mem_pd = __mem, \
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.get_power = __get_power, \
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}
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#define TOP_PD(__name, __top_pd, __mem, __get_power) \
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{ \
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.name = __name, \
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.top_pd = __top_pd, \
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.mem_pd_count = ARRAY_SIZE(__mem), \
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.mem_pd = __mem, \
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.get_power = __get_power, \
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}
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#define MEM_PD(__name, __mem) \
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TOP_PD(__name, NULL, __mem, NULL)
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static bool pwrc_ee_get_power(struct power_domain *power_domain);
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static struct meson_ee_pwrc_domain_desc g12a_pwrc_domains[] = {
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[PWRC_G12A_VPU_ID] = VPU_PD("VPU", &g12a_pwrc_vpu, g12a_pwrc_mem_vpu,
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pwrc_ee_get_power, 11, 2),
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[PWRC_G12A_ETH_ID] = MEM_PD("ETH", g12a_pwrc_mem_eth),
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};
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static struct meson_ee_pwrc_domain_desc sm1_pwrc_domains[] = {
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[PWRC_SM1_VPU_ID] = VPU_PD("VPU", &sm1_pwrc_vpu, sm1_pwrc_mem_vpu,
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pwrc_ee_get_power, 11, 2),
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[PWRC_SM1_NNA_ID] = TOP_PD("NNA", &sm1_pwrc_nna, sm1_pwrc_mem_nna,
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pwrc_ee_get_power),
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[PWRC_SM1_USB_ID] = TOP_PD("USB", &sm1_pwrc_usb, sm1_pwrc_mem_usb,
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pwrc_ee_get_power),
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[PWRC_SM1_PCIE_ID] = TOP_PD("PCI", &sm1_pwrc_pci, sm1_pwrc_mem_pcie,
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pwrc_ee_get_power),
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[PWRC_SM1_GE2D_ID] = TOP_PD("GE2D", &sm1_pwrc_ge2d, sm1_pwrc_mem_ge2d,
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pwrc_ee_get_power),
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[PWRC_SM1_AUDIO_ID] = MEM_PD("AUDIO", sm1_pwrc_mem_audio),
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[PWRC_SM1_ETH_ID] = MEM_PD("ETH", g12a_pwrc_mem_eth),
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};
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struct meson_ee_pwrc_priv {
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struct regmap *regmap_ao;
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struct regmap *regmap_hhi;
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struct reset_ctl_bulk resets;
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struct clk_bulk clks;
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const struct meson_ee_pwrc_domain_data *data;
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};
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static bool pwrc_ee_get_power(struct power_domain *power_domain)
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{
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struct meson_ee_pwrc_priv *priv = dev_get_priv(power_domain->dev);
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struct meson_ee_pwrc_domain_desc *pwrc_domain;
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u32 reg;
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pwrc_domain = &priv->data->domains[power_domain->id];
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regmap_read(priv->regmap_ao,
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pwrc_domain->top_pd->sleep_reg, ®);
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return (reg & pwrc_domain->top_pd->sleep_mask);
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}
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static int meson_ee_pwrc_request(struct power_domain *power_domain)
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{
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return 0;
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}
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static int meson_ee_pwrc_free(struct power_domain *power_domain)
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{
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return 0;
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}
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static int meson_ee_pwrc_off(struct power_domain *power_domain)
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{
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struct meson_ee_pwrc_priv *priv = dev_get_priv(power_domain->dev);
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struct meson_ee_pwrc_domain_desc *pwrc_domain;
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int i;
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pwrc_domain = &priv->data->domains[power_domain->id];
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if (pwrc_domain->top_pd)
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regmap_update_bits(priv->regmap_ao,
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pwrc_domain->top_pd->sleep_reg,
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pwrc_domain->top_pd->sleep_mask,
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pwrc_domain->top_pd->sleep_mask);
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udelay(20);
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for (i = 0 ; i < pwrc_domain->mem_pd_count ; ++i)
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regmap_update_bits(priv->regmap_hhi,
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pwrc_domain->mem_pd[i].reg,
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pwrc_domain->mem_pd[i].mask,
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pwrc_domain->mem_pd[i].mask);
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udelay(20);
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if (pwrc_domain->top_pd)
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regmap_update_bits(priv->regmap_ao,
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pwrc_domain->top_pd->iso_reg,
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pwrc_domain->top_pd->iso_mask,
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pwrc_domain->top_pd->iso_mask);
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if (pwrc_domain->clk_names_count) {
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mdelay(20);
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clk_disable_bulk(&priv->clks);
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}
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return 0;
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}
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static int meson_ee_pwrc_on(struct power_domain *power_domain)
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{
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struct meson_ee_pwrc_priv *priv = dev_get_priv(power_domain->dev);
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struct meson_ee_pwrc_domain_desc *pwrc_domain;
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int i, ret;
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pwrc_domain = &priv->data->domains[power_domain->id];
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if (pwrc_domain->top_pd)
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regmap_update_bits(priv->regmap_ao,
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pwrc_domain->top_pd->sleep_reg,
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pwrc_domain->top_pd->sleep_mask, 0);
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udelay(20);
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for (i = 0 ; i < pwrc_domain->mem_pd_count ; ++i)
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regmap_update_bits(priv->regmap_hhi,
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pwrc_domain->mem_pd[i].reg,
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pwrc_domain->mem_pd[i].mask, 0);
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udelay(20);
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if (pwrc_domain->reset_names_count) {
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ret = reset_assert_bulk(&priv->resets);
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if (ret)
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return ret;
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}
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if (pwrc_domain->top_pd)
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regmap_update_bits(priv->regmap_ao,
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pwrc_domain->top_pd->iso_reg,
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pwrc_domain->top_pd->iso_mask, 0);
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if (pwrc_domain->reset_names_count) {
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ret = reset_deassert_bulk(&priv->resets);
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if (ret)
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return ret;
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}
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if (pwrc_domain->clk_names_count)
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return clk_enable_bulk(&priv->clks);
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return 0;
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}
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static int meson_ee_pwrc_of_xlate(struct power_domain *power_domain,
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struct ofnode_phandle_args *args)
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{
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struct meson_ee_pwrc_priv *priv = dev_get_priv(power_domain->dev);
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/* #power-domain-cells is 1 */
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if (args->args_count < 1) {
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debug("Invalid args_count: %d\n", args->args_count);
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return -EINVAL;
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}
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power_domain->id = args->args[0];
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if (power_domain->id >= priv->data->count) {
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debug("Invalid domain ID: %lu\n", power_domain->id);
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return -EINVAL;
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}
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return 0;
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}
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struct power_domain_ops meson_ee_pwrc_ops = {
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.rfree = meson_ee_pwrc_free,
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.off = meson_ee_pwrc_off,
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.on = meson_ee_pwrc_on,
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.request = meson_ee_pwrc_request,
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.of_xlate = meson_ee_pwrc_of_xlate,
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};
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static struct meson_ee_pwrc_domain_data meson_ee_g12a_pwrc_data = {
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.count = ARRAY_SIZE(g12a_pwrc_domains),
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.domains = g12a_pwrc_domains,
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};
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static struct meson_ee_pwrc_domain_data meson_ee_sm1_pwrc_data = {
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.count = ARRAY_SIZE(sm1_pwrc_domains),
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.domains = sm1_pwrc_domains,
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};
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static const struct udevice_id meson_ee_pwrc_ids[] = {
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{
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.compatible = "amlogic,meson-g12a-pwrc",
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.data = (unsigned long)&meson_ee_g12a_pwrc_data,
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},
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{
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.compatible = "amlogic,meson-sm1-pwrc",
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.data = (unsigned long)&meson_ee_sm1_pwrc_data,
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},
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{ }
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};
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static int meson_ee_pwrc_probe(struct udevice *dev)
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{
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struct meson_ee_pwrc_priv *priv = dev_get_priv(dev);
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u32 ao_phandle;
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ofnode ao_node;
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int ret;
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priv->data = (void *)dev_get_driver_data(dev);
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if (!priv->data)
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return -EINVAL;
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priv->regmap_hhi = syscon_node_to_regmap(dev_get_parent(dev)->node);
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if (IS_ERR(priv->regmap_hhi))
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return PTR_ERR(priv->regmap_hhi);
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ret = ofnode_read_u32(dev->node, "amlogic,ao-sysctrl",
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&ao_phandle);
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if (ret)
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return ret;
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ao_node = ofnode_get_by_phandle(ao_phandle);
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if (!ofnode_valid(ao_node))
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return -EINVAL;
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priv->regmap_ao = syscon_node_to_regmap(ao_node);
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if (IS_ERR(priv->regmap_ao))
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return PTR_ERR(priv->regmap_ao);
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ret = reset_get_bulk(dev, &priv->resets);
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if (ret)
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return ret;
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ret = clk_get_bulk(dev, &priv->clks);
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if (ret)
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return ret;
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return 0;
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}
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U_BOOT_DRIVER(meson_ee_pwrc) = {
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.name = "meson_ee_pwrc",
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.id = UCLASS_POWER_DOMAIN,
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.of_match = meson_ee_pwrc_ids,
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.probe = meson_ee_pwrc_probe,
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.ops = &meson_ee_pwrc_ops,
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.priv_auto = sizeof(struct meson_ee_pwrc_priv),
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};
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