mirror of
https://github.com/brain-hackers/u-boot-brain
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caa4daa2ae
We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
106 lines
2.8 KiB
C
106 lines
2.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2018 Cisco Systems, Inc.
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* (C) Copyright 2019 Synamedia
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*
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* Author: Thomas Fitzsimmons <fitzsim@fitzsim.org>
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*/
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#include <common.h>
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#include <dm.h>
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#include <mach/sdhci.h>
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#include <malloc.h>
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#include <sdhci.h>
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/*
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* The BCMSTB SDHCI has a quirk in that its actual maximum frequency
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* capability is 100 MHz. The divisor that is eventually written to
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* SDHCI_CLOCK_CONTROL is calculated based on what the MMC device
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* reports, and relative to this maximum frequency.
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*
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* This define used to be set to 52000000 (52 MHz), the desired
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* maximum frequency, but that would result in the communication
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* actually running at 100 MHz (seemingly without issue), which is
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* out-of-spec.
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*
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* Now, by setting this to 0 (auto-detect), 100 MHz will be read from
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* the capabilities register, and the resulting divisor will be
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* doubled, meaning that the clock control register will be set to the
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* in-spec 52 MHz value.
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*/
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#define BCMSTB_SDHCI_MAXIMUM_CLOCK_FREQUENCY 0
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/*
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* When the minimum clock frequency is set to 0 (auto-detect), U-Boot
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* sets it to 100 MHz divided by SDHCI_MAX_DIV_SPEC_300, or 48,875 Hz,
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* which results in the controller timing out when trying to
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* communicate with the MMC device. Hard-code this value to 400000
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* (400 kHz) to prevent this.
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*/
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#define BCMSTB_SDHCI_MINIMUM_CLOCK_FREQUENCY 400000
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/*
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* This driver has only been tested with eMMC devices; SD devices may
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* not work.
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*/
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struct sdhci_bcmstb_plat {
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struct mmc_config cfg;
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struct mmc mmc;
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};
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static int sdhci_bcmstb_bind(struct udevice *dev)
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{
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struct sdhci_bcmstb_plat *plat = dev_get_platdata(dev);
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return sdhci_bind(dev, &plat->mmc, &plat->cfg);
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}
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static int sdhci_bcmstb_probe(struct udevice *dev)
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{
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struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
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struct sdhci_bcmstb_plat *plat = dev_get_platdata(dev);
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struct sdhci_host *host = dev_get_priv(dev);
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fdt_addr_t base;
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int ret;
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base = dev_read_addr(dev);
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if (base == FDT_ADDR_T_NONE)
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return -EINVAL;
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host->name = dev->name;
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host->ioaddr = (void *)base;
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ret = mmc_of_parse(dev, &plat->cfg);
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if (ret)
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return ret;
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host->mmc = &plat->mmc;
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host->mmc->dev = dev;
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ret = sdhci_setup_cfg(&plat->cfg, host,
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BCMSTB_SDHCI_MAXIMUM_CLOCK_FREQUENCY,
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BCMSTB_SDHCI_MINIMUM_CLOCK_FREQUENCY);
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if (ret)
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return ret;
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upriv->mmc = &plat->mmc;
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host->mmc->priv = host;
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return sdhci_probe(dev);
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}
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static const struct udevice_id sdhci_bcmstb_match[] = {
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{ .compatible = "brcm,bcm7425-sdhci" },
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{ .compatible = "brcm,sdhci-brcmstb" },
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{ }
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};
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U_BOOT_DRIVER(sdhci_bcmstb) = {
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.name = "sdhci-bcmstb",
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.id = UCLASS_MMC,
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.of_match = sdhci_bcmstb_match,
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.ops = &sdhci_ops,
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.bind = sdhci_bcmstb_bind,
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.probe = sdhci_bcmstb_probe,
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.priv_auto = sizeof(struct sdhci_host),
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.plat_auto = sizeof(struct sdhci_bcmstb_plat),
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};
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