319 lines
10 KiB
C
319 lines
10 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2017 Intel Corporation.
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* Copyright 2019 Google LLC
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*
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* Modified from coreboot gpio.h
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*/
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#ifndef __ASM_INTEL_PINCTRL_H
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#define __ASM_INTEL_PINCTRL_H
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#include <dm/pinctrl.h>
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#include <linux/bitops.h>
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/**
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* struct pad_config - config for a pad
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* @pad: offset of pad within community
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* @pad_config: Pad config data corresponding to DW0, DW1, etc.
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*/
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struct pad_config {
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int pad;
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u32 pad_config[4];
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};
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#include <asm/arch/gpio.h>
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/* GPIO community IOSF sideband clock gating */
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#define MISCCFG_GPSIDEDPCGEN BIT(5)
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/* GPIO community RCOMP clock gating */
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#define MISCCFG_GPRCOMPCDLCGEN BIT(4)
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/* GPIO community RTC clock gating */
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#define MISCCFG_GPRTCDLCGEN BIT(3)
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/* GFX controller clock gating */
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#define MISCCFG_GSXSLCGEN BIT(2)
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/* GPIO community partition clock gating */
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#define MISCCFG_GPDPCGEN BIT(1)
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/* GPIO community local clock gating */
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#define MISCCFG_GPDLCGEN BIT(0)
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/* Enable GPIO community power management configuration */
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#define MISCCFG_ENABLE_GPIO_PM_CONFIG (MISCCFG_GPSIDEDPCGEN | \
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MISCCFG_GPRCOMPCDLCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN \
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| MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN)
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/*
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* GPIO numbers may not be contiguous and instead will have a different
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* starting pin number for each pad group.
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*/
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#define INTEL_GPP_BASE(first_of_community, start_of_group, end_of_group,\
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group_pad_base) \
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{ \
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.first_pad = (start_of_group) - (first_of_community), \
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.size = (end_of_group) - (start_of_group) + 1, \
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.acpi_pad_base = (group_pad_base), \
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}
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/*
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* A pad base of -1 indicates that this group uses contiguous numbering
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* and a pad base should not be used for this group.
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*/
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#define PAD_BASE_NONE -1
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/* The common/default group numbering is contiguous */
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#define INTEL_GPP(first_of_community, start_of_group, end_of_group) \
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INTEL_GPP_BASE(first_of_community, start_of_group, end_of_group,\
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PAD_BASE_NONE)
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/**
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* struct reset_mapping - logical to actual value for PADRSTCFG in DW0
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*
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* Note that the values are expected to be within the field placement of the
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* register itself. i.e. if the reset field is at 31:30 then the values within
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* logical and chipset should occupy 31:30.
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*/
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struct reset_mapping {
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u32 logical;
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u32 chipset;
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};
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/**
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* struct pad_group - describes the groups within each community
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*
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* @first_pad: offset of first pad of the group relative to the community
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* @size: size of the group
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* @acpi_pad_base: starting pin number for the pads in this group when they are
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* used in ACPI. This is only needed if the pins are not contiguous across
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* groups. Most groups will have this set to PAD_BASE_NONE and use
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* contiguous numbering for ACPI.
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*/
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struct pad_group {
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int first_pad;
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uint size;
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int acpi_pad_base;
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};
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/**
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* struct pad_community - community of pads
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*
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* This describes a community, or each group within a community when multiple
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* groups exist inside a community
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*
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* @name: Community name
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* @num_gpi_regs: number of gpi registers in community
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* @max_pads_per_group: number of pads in each group; number of pads bit-mapped
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* in each GPI status/en and Host Own Reg
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* @first_pad: first pad in community
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* @last_pad: last pad in community
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* @host_own_reg_0: offset to Host Ownership Reg 0
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* @gpi_int_sts_reg_0: offset to GPI Int STS Reg 0
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* @gpi_int_en_reg_0: offset to GPI Int Enable Reg 0
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* @gpi_smi_sts_reg_0: offset to GPI SMI STS Reg 0
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* @gpi_smi_en_reg_0: offset to GPI SMI EN Reg 0
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* @pad_cfg_base: offset to first PAD_GFG_DW0 Reg
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* @gpi_status_offset: specifies offset in struct gpi_status
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* @port: PCR Port ID
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* @reset_map: PADRSTCFG logical to chipset mapping
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* @num_reset_vals: number of values in @reset_map
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* @groups; list of groups for this community
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* @num_groups: number of groups
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*/
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struct pad_community {
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const char *name;
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size_t num_gpi_regs;
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size_t max_pads_per_group;
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uint first_pad;
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uint last_pad;
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u16 host_own_reg_0;
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u16 gpi_int_sts_reg_0;
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u16 gpi_int_en_reg_0;
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u16 gpi_smi_sts_reg_0;
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u16 gpi_smi_en_reg_0;
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u16 pad_cfg_base;
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u8 gpi_status_offset;
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u8 port;
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const struct reset_mapping *reset_map;
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size_t num_reset_vals;
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const struct pad_group *groups;
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size_t num_groups;
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};
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/**
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* struct intel_pinctrl_priv - private data for each pinctrl device
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*
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* @comm: Pad community for this device
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* @num_cfgs: Number of configuration words for each pad
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* @itss: ITSS device (for interrupt handling)
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* @itss_pol_cfg: Use to program Interrupt Polarity Control (IPCx) register
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* Each bit represents IRQx Active High Polarity Disable configuration:
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* when set to 1, the interrupt polarity associated with IRQx is inverted
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* to appear as Active Low to IOAPIC and vice versa
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*/
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struct intel_pinctrl_priv {
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const struct pad_community *comm;
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int num_cfgs;
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struct udevice *itss;
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bool itss_pol_cfg;
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};
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/* Exported common operations for the pinctrl driver */
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extern const struct pinctrl_ops intel_pinctrl_ops;
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/* Exported common probe function for the pinctrl driver */
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int intel_pinctrl_probe(struct udevice *dev);
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/**
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* intel_pinctrl_ofdata_to_platdata() - Handle common plat setup
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*
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* @dev: Pinctrl device
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* @comm: Pad community for this device
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* @num_cfgs: Number of configuration words for each pad
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* @return 0 if OK, -EDOM if @comm is NULL, other -ve value on other error
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*/
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int intel_pinctrl_ofdata_to_platdata(struct udevice *dev,
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const struct pad_community *comm,
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int num_cfgs);
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/**
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* pinctrl_route_gpe() - set GPIO groups for the general-purpose-event blocks
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*
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* The values from PMC register GPE_CFG are passed which is then mapped to
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* proper groups for MISCCFG. This basically sets the MISCCFG register bits:
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* dw0 = gpe0_route[11:8]. This is ACPI GPE0b.
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* dw1 = gpe0_route[15:12]. This is ACPI GPE0c.
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* dw2 = gpe0_route[19:16]. This is ACPI GPE0d.
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*
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* @dev: ITSS device
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* @gpe0b: Value for GPE0B
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* @gpe0c: Value for GPE0C
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* @gpe0d: Value for GPE0D
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* @return 0 if OK, -ve on error
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*/
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int pinctrl_route_gpe(struct udevice *dev, uint gpe0b, uint gpe0c, uint gpe0d);
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/**
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* pinctrl_config_pads() - Configure a list of pads
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*
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* Configures multiple pads using the provided data from the device tree.
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*
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* @dev: pinctrl device (any will do)
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* @pads: Pad data, consisting of a pad number followed by num_cfgs entries
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* containing the data for that pad (num_cfgs is set by the pinctrl device)
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* @pads_count: Number of pads to configure
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* @return 0 if OK, -ve on error
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*/
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int pinctrl_config_pads(struct udevice *dev, u32 *pads, int pads_count);
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/**
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* pinctrl_gpi_clear_int_cfg() - Set up the interrupts for use
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*
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* This enables the interrupt inputs and clears the status register bits
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*
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* @return 0 if OK, -ve on error
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*/
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int pinctrl_gpi_clear_int_cfg(void);
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/**
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* pinctrl_config_pads_for_node() - Configure pads
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*
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* Set up the pads using the data in a given node
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*
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* @dev: pinctrl device (any will do)
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* @node: Node containing the 'pads' property with the data in it
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* @return 0 if OK, -ve on error
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*/
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int pinctrl_config_pads_for_node(struct udevice *dev, ofnode node);
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/**
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* pinctrl_read_pads() - Read pad data from a node
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*
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* @dev: pinctrl device (any will do, it is just used to get config)
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* @node: Node to read pad data from
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* @prop: Property name to use (e.g. "pads")
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* @padsp: Returns a pointer to an allocated array of pad data, in the format:
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* <pad>
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* <pad_config0>
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* <pad_config1>
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* ...
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*
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* The number of pad config values is set by the pinctrl controller.
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* The caller must free this array.
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* @pad_countp: Returns the number of pads read
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* @ereturn 0 if OK, -ve on error
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*/
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int pinctrl_read_pads(struct udevice *dev, ofnode node, const char *prop,
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u32 **padsp, int *pad_countp);
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/**
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* pinctrl_count_pads() - Count the number of pads in a pad array
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*
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* This used used with of-platdata where the array may be smaller than its
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* maximum size. This function searches for the last pad in the array by finding
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* the first 'zero' record
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*
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* This works out the number of records in the array. Each record has one word
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* for the pad and num_cfgs words for the config.
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*
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* @dev: pinctrl device (any will do)
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* @pads: Array of pad data
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* @size: Size of pad data in bytes
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* @return number of pads represented by the data
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*/
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int pinctrl_count_pads(struct udevice *dev, u32 *pads, int size);
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/**
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* intel_pinctrl_get_config_reg_offset() - Get offset of pin config registers
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*
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* This works out the register offset of a pin within the p2sb region.
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*
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* @dev: Pinctrl device
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* @offset: GPIO offset within this device
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* @return register offset of first register within the GPIO p2sb region
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*/
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u32 intel_pinctrl_get_config_reg_offset(struct udevice *dev, uint offset);
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/**
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* intel_pinctrl_get_config_reg_addr() - Get address of pin config registers
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*
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* This works out the absolute address of the registers for a pin
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* @dev: Pinctrl device
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* @offset: GPIO offset within this device
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* @return register address of first register within the GPIO p2sb region
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*/
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u32 intel_pinctrl_get_config_reg_addr(struct udevice *dev, uint offset);
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/**
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* intel_pinctrl_get_config_reg() - Get the value of a GPIO register
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*
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* @dev: Pinctrl device
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* @offset: GPIO offset within this device
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* @return register value within the GPIO p2sb region
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*/
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u32 intel_pinctrl_get_config_reg(struct udevice *dev, uint offset);
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/**
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* intel_pinctrl_get_pad() - Get pad information for a pad
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*
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* This is used by the GPIO controller to find the pinctrl used by a pad.
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*
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* @pad: Pad to check
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* @devp: Returns pinctrl device containing that pad
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* @offsetp: Returns offset of pad within that pinctrl device
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* @return 0 if OK, -ENOTBLK if pad number is invalid
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*/
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int intel_pinctrl_get_pad(uint pad, struct udevice **devp, uint *offsetp);
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/**
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* intel_pinctrl_get_acpi_pin() - Get the ACPI pin for a pinctrl pin
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*
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* Maps a pinctrl pin (in terms of its offset within the pins controlled by that
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* pinctrl) to an ACPI GPIO pin-table entry.
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*
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* @dev: Pinctrl device to check
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* @offset: Offset of pin within that device (0 = first)
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* @return associated ACPI GPIO pin-table entry, or standard pin number if the
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* ACPI pad base is not set
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*/
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int intel_pinctrl_get_acpi_pin(struct udevice *dev, uint offset);
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#endif
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