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https://github.com/brain-hackers/u-boot-brain
synced 2024-08-28 21:09:00 +09:00
![Pantelis Antoniou](/assets/img/avatar_default.png)
The way that struct mmc was implemented was a bit of a mess; configuration and internal state all jumbled up in a single structure. On top of that the way initialization is done with mmc_register leads to a lot of duplicated code in drivers. Typically the initialization got something like this in every driver. struct mmc *mmc = malloc(sizeof(struct mmc)); memset(mmc, 0, sizeof(struct mmc); /* fill in fields of mmc struct */ /* store private data pointer */ mmc_register(mmc); By using the new mmc_create call one just passes an mmc config struct and an optional private data pointer like this: struct mmc = mmc_create(&cfg, priv); All in tree drivers have been updated to the new form, and expect mmc_register to go away before long. Changes since v1: * Use calloc instead of manually calling memset. * Mark mmc_register as deprecated. Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
374 lines
8.2 KiB
C
374 lines
8.2 KiB
C
/*
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* Faraday MMC/SD Host Controller
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*
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* (C) Copyright 2010 Faraday Technology
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* Dante Su <dantesu@faraday-tech.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <malloc.h>
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#include <part.h>
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#include <mmc.h>
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#include <asm/io.h>
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#include <asm/errno.h>
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#include <asm/byteorder.h>
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#include <faraday/ftsdc010.h>
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#define CFG_CMD_TIMEOUT (CONFIG_SYS_HZ >> 4) /* 250 ms */
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#define CFG_RST_TIMEOUT CONFIG_SYS_HZ /* 1 sec reset timeout */
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struct ftsdc010_chip {
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void __iomem *regs;
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uint32_t wprot; /* write protected (locked) */
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uint32_t rate; /* actual SD clock in Hz */
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uint32_t sclk; /* FTSDC010 source clock in Hz */
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uint32_t fifo; /* fifo depth in bytes */
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uint32_t acmd;
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struct mmc_config cfg; /* mmc configuration */
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};
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static inline int ftsdc010_send_cmd(struct mmc *mmc, struct mmc_cmd *mmc_cmd)
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{
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struct ftsdc010_chip *chip = mmc->priv;
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struct ftsdc010_mmc __iomem *regs = chip->regs;
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int ret = TIMEOUT;
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uint32_t ts, st;
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uint32_t cmd = FTSDC010_CMD_IDX(mmc_cmd->cmdidx);
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uint32_t arg = mmc_cmd->cmdarg;
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uint32_t flags = mmc_cmd->resp_type;
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cmd |= FTSDC010_CMD_CMD_EN;
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if (chip->acmd) {
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cmd |= FTSDC010_CMD_APP_CMD;
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chip->acmd = 0;
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}
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if (flags & MMC_RSP_PRESENT)
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cmd |= FTSDC010_CMD_NEED_RSP;
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if (flags & MMC_RSP_136)
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cmd |= FTSDC010_CMD_LONG_RSP;
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writel(FTSDC010_STATUS_RSP_MASK | FTSDC010_STATUS_CMD_SEND,
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®s->clr);
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writel(arg, ®s->argu);
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writel(cmd, ®s->cmd);
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if (!(flags & (MMC_RSP_PRESENT | MMC_RSP_136))) {
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for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) {
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if (readl(®s->status) & FTSDC010_STATUS_CMD_SEND) {
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writel(FTSDC010_STATUS_CMD_SEND, ®s->clr);
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ret = 0;
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break;
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}
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}
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} else {
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st = 0;
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for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) {
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st = readl(®s->status);
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writel(st & FTSDC010_STATUS_RSP_MASK, ®s->clr);
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if (st & FTSDC010_STATUS_RSP_MASK)
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break;
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}
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if (st & FTSDC010_STATUS_RSP_CRC_OK) {
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if (flags & MMC_RSP_136) {
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mmc_cmd->response[0] = readl(®s->rsp3);
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mmc_cmd->response[1] = readl(®s->rsp2);
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mmc_cmd->response[2] = readl(®s->rsp1);
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mmc_cmd->response[3] = readl(®s->rsp0);
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} else {
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mmc_cmd->response[0] = readl(®s->rsp0);
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}
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ret = 0;
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} else {
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debug("ftsdc010: rsp err (cmd=%d, st=0x%x)\n",
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mmc_cmd->cmdidx, st);
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}
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}
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if (ret) {
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debug("ftsdc010: cmd timeout (op code=%d)\n",
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mmc_cmd->cmdidx);
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} else if (mmc_cmd->cmdidx == MMC_CMD_APP_CMD) {
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chip->acmd = 1;
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}
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return ret;
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}
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static void ftsdc010_clkset(struct mmc *mmc, uint32_t rate)
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{
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struct ftsdc010_chip *chip = mmc->priv;
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struct ftsdc010_mmc __iomem *regs = chip->regs;
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uint32_t div;
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for (div = 0; div < 0x7f; ++div) {
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if (rate >= chip->sclk / (2 * (div + 1)))
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break;
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}
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chip->rate = chip->sclk / (2 * (div + 1));
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writel(FTSDC010_CCR_CLK_DIV(div), ®s->ccr);
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if (IS_SD(mmc)) {
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setbits_le32(®s->ccr, FTSDC010_CCR_CLK_SD);
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if (chip->rate > 25000000)
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setbits_le32(®s->ccr, FTSDC010_CCR_CLK_HISPD);
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else
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clrbits_le32(®s->ccr, FTSDC010_CCR_CLK_HISPD);
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}
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}
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static int ftsdc010_wait(struct ftsdc010_mmc __iomem *regs, uint32_t mask)
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{
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int ret = TIMEOUT;
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uint32_t st, ts;
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for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) {
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st = readl(®s->status);
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if (!(st & mask))
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continue;
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writel(st & mask, ®s->clr);
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ret = 0;
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break;
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}
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if (ret)
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debug("ftsdc010: wait st(0x%x) timeout\n", mask);
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return ret;
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}
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/*
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* u-boot mmc api
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*/
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static int ftsdc010_request(struct mmc *mmc, struct mmc_cmd *cmd,
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struct mmc_data *data)
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{
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int ret = UNUSABLE_ERR;
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uint32_t len = 0;
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struct ftsdc010_chip *chip = mmc->priv;
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struct ftsdc010_mmc __iomem *regs = chip->regs;
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if (data && (data->flags & MMC_DATA_WRITE) && chip->wprot) {
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printf("ftsdc010: the card is write protected!\n");
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return ret;
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}
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if (data) {
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uint32_t dcr;
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len = data->blocksize * data->blocks;
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/* 1. data disable + fifo reset */
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dcr = 0;
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#ifdef CONFIG_FTSDC010_SDIO
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dcr |= FTSDC010_DCR_FIFO_RST;
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#endif
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writel(dcr, ®s->dcr);
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/* 2. clear status register */
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writel(FTSDC010_STATUS_DATA_MASK | FTSDC010_STATUS_FIFO_URUN
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| FTSDC010_STATUS_FIFO_ORUN, ®s->clr);
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/* 3. data timeout (1 sec) */
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writel(chip->rate, ®s->dtr);
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/* 4. data length (bytes) */
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writel(len, ®s->dlr);
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/* 5. data enable */
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dcr = (ffs(data->blocksize) - 1) | FTSDC010_DCR_DATA_EN;
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if (data->flags & MMC_DATA_WRITE)
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dcr |= FTSDC010_DCR_DATA_WRITE;
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writel(dcr, ®s->dcr);
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}
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ret = ftsdc010_send_cmd(mmc, cmd);
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if (ret) {
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printf("ftsdc010: CMD%d failed\n", cmd->cmdidx);
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return ret;
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}
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if (!data)
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return ret;
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if (data->flags & MMC_DATA_WRITE) {
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const uint8_t *buf = (const uint8_t *)data->src;
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while (len > 0) {
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int wlen;
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/* wait for tx ready */
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ret = ftsdc010_wait(regs, FTSDC010_STATUS_FIFO_URUN);
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if (ret)
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break;
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/* write bytes to ftsdc010 */
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for (wlen = 0; wlen < len && wlen < chip->fifo; ) {
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writel(*(uint32_t *)buf, ®s->dwr);
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buf += 4;
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wlen += 4;
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}
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len -= wlen;
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}
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} else {
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uint8_t *buf = (uint8_t *)data->dest;
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while (len > 0) {
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int rlen;
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/* wait for rx ready */
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ret = ftsdc010_wait(regs, FTSDC010_STATUS_FIFO_ORUN);
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if (ret)
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break;
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/* fetch bytes from ftsdc010 */
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for (rlen = 0; rlen < len && rlen < chip->fifo; ) {
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*(uint32_t *)buf = readl(®s->dwr);
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buf += 4;
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rlen += 4;
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}
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len -= rlen;
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}
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}
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if (!ret) {
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ret = ftsdc010_wait(regs,
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FTSDC010_STATUS_DATA_END | FTSDC010_STATUS_DATA_ERROR);
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}
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return ret;
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}
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static void ftsdc010_set_ios(struct mmc *mmc)
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{
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struct ftsdc010_chip *chip = mmc->priv;
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struct ftsdc010_mmc __iomem *regs = chip->regs;
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ftsdc010_clkset(mmc, mmc->clock);
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clrbits_le32(®s->bwr, FTSDC010_BWR_MODE_MASK);
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switch (mmc->bus_width) {
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case 4:
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setbits_le32(®s->bwr, FTSDC010_BWR_MODE_4BIT);
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break;
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case 8:
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setbits_le32(®s->bwr, FTSDC010_BWR_MODE_8BIT);
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break;
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default:
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setbits_le32(®s->bwr, FTSDC010_BWR_MODE_1BIT);
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break;
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}
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}
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static int ftsdc010_init(struct mmc *mmc)
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{
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struct ftsdc010_chip *chip = mmc->priv;
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struct ftsdc010_mmc __iomem *regs = chip->regs;
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uint32_t ts;
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if (readl(®s->status) & FTSDC010_STATUS_CARD_DETECT)
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return NO_CARD_ERR;
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if (readl(®s->status) & FTSDC010_STATUS_WRITE_PROT) {
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printf("ftsdc010: write protected\n");
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chip->wprot = 1;
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}
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chip->fifo = (readl(®s->feature) & 0xff) << 2;
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/* 1. chip reset */
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writel(FTSDC010_CMD_SDC_RST, ®s->cmd);
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for (ts = get_timer(0); get_timer(ts) < CFG_RST_TIMEOUT; ) {
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if (readl(®s->cmd) & FTSDC010_CMD_SDC_RST)
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continue;
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break;
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}
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if (readl(®s->cmd) & FTSDC010_CMD_SDC_RST) {
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printf("ftsdc010: reset failed\n");
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return UNUSABLE_ERR;
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}
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/* 2. enter low speed mode (400k card detection) */
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ftsdc010_clkset(mmc, 400000);
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/* 3. interrupt disabled */
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writel(0, ®s->int_mask);
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return 0;
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}
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static const struct mmc_ops ftsdc010_ops = {
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.send_cmd = ftsdc010_request,
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.set_ios = ftsdc010_set_ios,
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.init = ftsdc010_init,
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};
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int ftsdc010_mmc_init(int devid)
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{
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struct mmc *mmc;
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struct ftsdc010_chip *chip;
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struct ftsdc010_mmc __iomem *regs;
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#ifdef CONFIG_FTSDC010_BASE_LIST
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uint32_t base_list[] = CONFIG_FTSDC010_BASE_LIST;
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if (devid < 0 || devid >= ARRAY_SIZE(base_list))
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return -1;
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regs = (void __iomem *)base_list[devid];
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#else
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regs = (void __iomem *)(CONFIG_FTSDC010_BASE + (devid << 20));
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#endif
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chip = malloc(sizeof(struct ftsdc010_chip));
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if (!chip)
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return -ENOMEM;
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memset(chip, 0, sizeof(struct ftsdc010_chip));
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chip->regs = regs;
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#ifdef CONFIG_SYS_CLK_FREQ
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chip->sclk = CONFIG_SYS_CLK_FREQ;
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#else
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chip->sclk = clk_get_rate("SDC");
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#endif
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chip->cfg.name = "ftsdc010";
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chip->cfg.ops = &ftsdc010_ops;
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chip->cfg.host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz;
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switch (readl(®s->bwr) & FTSDC010_BWR_CAPS_MASK) {
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case FTSDC010_BWR_CAPS_4BIT:
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chip->cfg.host_caps |= MMC_MODE_4BIT;
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break;
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case FTSDC010_BWR_CAPS_8BIT:
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chip->cfg.host_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
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break;
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default:
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break;
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}
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chip->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
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chip->cfg.f_max = chip->sclk / 2;
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chip->cfg.f_min = chip->sclk / 0x100;
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chip->cfg.part_type = PART_TYPE_DOS;
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chip->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
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mmc = mmc_create(&chip->cfg, chip);
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if (mmc == NULL) {
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free(chip);
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return -ENOMEM;
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}
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return 0;
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}
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