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![Rajeshwari S Shinde](/assets/img/avatar_default.png)
This patch corrects the divider value written to CLKDIV register. Since SDCLKIN is divided inside controller by the DIVRATIO value set in the CLKSEL register, we need to use the same output clock value to calculate the CLKDIV value. as per user manual: cclk_in = SDCLKIN / (DIVRATIO + 1) Input parameter to mmc_clk is changed to dwmci_host, since we need the same to read DWMCI_CLKSEL register. This improves the read timing values for channel 0 on SMDK5250 from 0.288sec to 0.144sec Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
182 lines
4.7 KiB
C
182 lines
4.7 KiB
C
/*
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* (C) Copyright 2012 SAMSUNG Electronics
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* Jaehoon Chung <jh80.chung@samsung.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dwmmc.h>
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#include <fdtdec.h>
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#include <libfdt.h>
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#include <malloc.h>
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#include <asm/arch/dwmmc.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/pinmux.h>
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#define DWMMC_MAX_CH_NUM 4
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#define DWMMC_MAX_FREQ 52000000
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#define DWMMC_MIN_FREQ 400000
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#define DWMMC_MMC0_CLKSEL_VAL 0x03030001
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#define DWMMC_MMC2_CLKSEL_VAL 0x03020001
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/*
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* Function used as callback function to initialise the
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* CLKSEL register for every mmc channel.
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*/
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static void exynos_dwmci_clksel(struct dwmci_host *host)
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{
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dwmci_writel(host, DWMCI_CLKSEL, host->clksel_val);
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}
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unsigned int exynos_dwmci_get_clk(struct dwmci_host *host)
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{
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unsigned long sclk;
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int8_t clk_div;
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/*
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* Since SDCLKIN is divided inside controller by the DIVRATIO
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* value set in the CLKSEL register, we need to use the same output
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* clock value to calculate the CLKDIV value.
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* as per user manual:cclk_in = SDCLKIN / (DIVRATIO + 1)
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*/
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clk_div = ((dwmci_readl(host, DWMCI_CLKSEL) >> DWMCI_DIVRATIO_BIT)
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& DWMCI_DIVRATIO_MASK) + 1;
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sclk = get_mmc_clk(host->dev_index);
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return sclk / clk_div;
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}
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static void exynos_dwmci_board_init(struct dwmci_host *host)
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{
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if (host->quirks & DWMCI_QUIRK_DISABLE_SMU) {
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dwmci_writel(host, EMMCP_MPSBEGIN0, 0);
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dwmci_writel(host, EMMCP_SEND0, 0);
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dwmci_writel(host, EMMCP_CTRL0,
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MPSCTRL_SECURE_READ_BIT |
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MPSCTRL_SECURE_WRITE_BIT |
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MPSCTRL_NON_SECURE_READ_BIT |
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MPSCTRL_NON_SECURE_WRITE_BIT | MPSCTRL_VALID);
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}
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}
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/*
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* This function adds the mmc channel to be registered with mmc core.
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* index - mmc channel number.
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* regbase - register base address of mmc channel specified in 'index'.
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* bus_width - operating bus width of mmc channel specified in 'index'.
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* clksel - value to be written into CLKSEL register in case of FDT.
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* NULL in case od non-FDT.
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*/
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int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel)
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{
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struct dwmci_host *host = NULL;
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unsigned int div;
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unsigned long freq, sclk;
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host = malloc(sizeof(struct dwmci_host));
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if (!host) {
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printf("dwmci_host malloc fail!\n");
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return 1;
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}
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/* request mmc clock vlaue of 52MHz. */
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freq = 52000000;
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sclk = get_mmc_clk(index);
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div = DIV_ROUND_UP(sclk, freq);
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/* set the clock divisor for mmc */
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set_mmc_clk(index, div);
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host->name = "EXYNOS DWMMC";
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host->ioaddr = (void *)regbase;
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host->buswidth = bus_width;
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#ifdef CONFIG_EXYNOS5420
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host->quirks = DWMCI_QUIRK_DISABLE_SMU;
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#endif
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host->board_init = exynos_dwmci_board_init;
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if (clksel) {
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host->clksel_val = clksel;
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} else {
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if (0 == index)
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host->clksel_val = DWMMC_MMC0_CLKSEL_VAL;
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if (2 == index)
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host->clksel_val = DWMMC_MMC2_CLKSEL_VAL;
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}
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host->clksel = exynos_dwmci_clksel;
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host->dev_index = index;
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host->get_mmc_clk = exynos_dwmci_get_clk;
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/* Add the mmc channel to be registered with mmc core */
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if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) {
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debug("dwmmc%d registration failed\n", index);
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return -1;
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}
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return 0;
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}
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#ifdef CONFIG_OF_CONTROL
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int exynos_dwmmc_init(const void *blob)
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{
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int index, bus_width;
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int node_list[DWMMC_MAX_CH_NUM];
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int err = 0, dev_id, flag, count, i;
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u32 clksel_val, base, timing[3];
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count = fdtdec_find_aliases_for_id(blob, "mmc",
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COMPAT_SAMSUNG_EXYNOS5_DWMMC, node_list,
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DWMMC_MAX_CH_NUM);
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for (i = 0; i < count; i++) {
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int node = node_list[i];
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if (node <= 0)
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continue;
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/* Extract device id for each mmc channel */
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dev_id = pinmux_decode_periph_id(blob, node);
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/* Get the bus width from the device node */
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bus_width = fdtdec_get_int(blob, node, "samsung,bus-width", 0);
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if (bus_width <= 0) {
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debug("DWMMC: Can't get bus-width\n");
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return -1;
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}
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if (8 == bus_width)
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flag = PINMUX_FLAG_8BIT_MODE;
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else
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flag = PINMUX_FLAG_NONE;
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/* config pinmux for each mmc channel */
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err = exynos_pinmux_config(dev_id, flag);
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if (err) {
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debug("DWMMC not configured\n");
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return err;
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}
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index = dev_id - PERIPH_ID_SDMMC0;
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/* Get the base address from the device node */
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base = fdtdec_get_addr(blob, node, "reg");
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if (!base) {
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debug("DWMMC: Can't get base address\n");
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return -1;
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}
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/* Extract the timing info from the node */
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err = fdtdec_get_int_array(blob, node, "samsung,timing",
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timing, 3);
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if (err) {
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debug("Can't get sdr-timings for divider\n");
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return -1;
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}
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clksel_val = (DWMCI_SET_SAMPLE_CLK(timing[0]) |
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DWMCI_SET_DRV_CLK(timing[1]) |
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DWMCI_SET_DIV_RATIO(timing[2]));
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/* Initialise each mmc channel */
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err = exynos_dwmci_add_port(index, base, bus_width, clksel_val);
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if (err)
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debug("dwmmc Channel-%d init failed\n", index);
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}
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return 0;
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}
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#endif
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