mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-31 14:28:52 +09:00
![Marek Vasut](/assets/img/avatar_default.png)
Both the RAVB and SH ether driver now support parsing the PHY reset GPIOs from both the PHY nodes and the MAC nodes, move the reset GPIOs back into the PHY nodes to minimize DT difference between U-Boot and Linux. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
124 lines
2.1 KiB
Plaintext
124 lines
2.1 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
|
|
/*
|
|
* Device Tree Source for the Eagle board
|
|
*
|
|
* Copyright (C) 2016-2017 Renesas Electronics Corp.
|
|
* Copyright (C) 2017 Cogent Embedded, Inc.
|
|
*/
|
|
|
|
/dts-v1/;
|
|
#include "r8a77970.dtsi"
|
|
#include <dt-bindings/gpio/gpio.h>
|
|
|
|
/ {
|
|
model = "Renesas Eagle board based on r8a77970";
|
|
compatible = "renesas,eagle", "renesas,r8a77970";
|
|
|
|
aliases {
|
|
serial0 = &scif0;
|
|
ethernet0 = &avb;
|
|
spi0 = &rpc;
|
|
};
|
|
|
|
chosen {
|
|
bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
|
|
stdout-path = "serial0:115200n8";
|
|
};
|
|
|
|
memory@48000000 {
|
|
device_type = "memory";
|
|
/* first 128MB is reserved for secure area. */
|
|
reg = <0x0 0x48000000 0x0 0x38000000>;
|
|
};
|
|
};
|
|
|
|
&avb {
|
|
pinctrl-0 = <&avb0_pins>;
|
|
pinctrl-names = "default";
|
|
renesas,no-ether-link;
|
|
phy-handle = <&phy0>;
|
|
phy-mode = "rgmii-id";
|
|
status = "okay";
|
|
|
|
phy0: ethernet-phy@0 {
|
|
rxc-skew-ps = <1500>;
|
|
reg = <0>;
|
|
interrupt-parent = <&gpio1>;
|
|
interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
|
|
reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
|
|
};
|
|
};
|
|
|
|
&extal_clk {
|
|
clock-frequency = <16666666>;
|
|
};
|
|
|
|
&extalr_clk {
|
|
clock-frequency = <32768>;
|
|
};
|
|
|
|
&i2c0 {
|
|
pinctrl-0 = <&i2c0_pins>;
|
|
pinctrl-names = "default";
|
|
|
|
status = "okay";
|
|
clock-frequency = <400000>;
|
|
|
|
io_expander: gpio@20 {
|
|
compatible = "onnn,pca9654";
|
|
reg = <0x20>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
};
|
|
};
|
|
|
|
&pfc {
|
|
avb0_pins: avb {
|
|
mux {
|
|
groups = "avb0_link", "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk";
|
|
function = "avb0";
|
|
};
|
|
};
|
|
|
|
i2c0_pins: i2c0 {
|
|
groups = "i2c0";
|
|
function = "i2c0";
|
|
};
|
|
|
|
scif0_pins: scif0 {
|
|
groups = "scif0_data";
|
|
function = "scif0";
|
|
};
|
|
};
|
|
|
|
&rpc {
|
|
num-cs = <1>;
|
|
status = "okay";
|
|
spi-max-frequency = <50000000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
flash0: spi-flash@0 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "s25fs512s", "spi-flash", "jedec,spi-nor";
|
|
spi-max-frequency = <50000000>;
|
|
spi-tx-bus-width = <1>;
|
|
spi-rx-bus-width = <1>;
|
|
reg = <0>;
|
|
status = "okay";
|
|
};
|
|
};
|
|
|
|
&rwdt {
|
|
timeout-sec = <60>;
|
|
status = "okay";
|
|
};
|
|
|
|
&scif0 {
|
|
pinctrl-0 = <&scif0_pins>;
|
|
pinctrl-names = "default";
|
|
|
|
status = "okay";
|
|
};
|