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![Shivamurthy Shastri](/assets/img/avatar_default.png)
Add SPINAND_HAS_CR_FEAT_BIT flag to identify the SPI NAND device with the Continuous Read mode. Some of the Micron SPI NAND devices have the "Continuous Read" feature enabled by default, which does not fit the subsystem needs. In this mode, the READ CACHE command doesn't require the starting column address. The device always output the data starting from the first column of the cache register, and once the end of the cache register reached, the data output continues through the next page. With the continuous read mode, it is possible to read out the entire block using a single READ command, and once the end of the block reached, the output pins become High-Z state. However, during this mode the read command doesn't output the OOB area. Hence, we disable the feature at probe time. Signed-off-by: Shivamurthy Shastri <sshivamurthy@micron.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
436 lines
13 KiB
C
436 lines
13 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2016-2017 Micron Technology, Inc.
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*
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* Authors:
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* Peter Pan <peterpandong@micron.com>
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*/
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#ifndef __LINUX_MTD_SPINAND_H
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#define __LINUX_MTD_SPINAND_H
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#ifndef __UBOOT__
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#include <linux/mutex.h>
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#include <linux/bitops.h>
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#include <linux/device.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/spi-mem.h>
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#else
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#include <common.h>
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#include <spi.h>
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#include <spi-mem.h>
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#include <linux/mtd/nand.h>
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#endif
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/**
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* Standard SPI NAND flash operations
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*/
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#define SPINAND_RESET_OP \
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SPI_MEM_OP(SPI_MEM_OP_CMD(0xff, 1), \
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SPI_MEM_OP_NO_ADDR, \
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SPI_MEM_OP_NO_DUMMY, \
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SPI_MEM_OP_NO_DATA)
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#define SPINAND_WR_EN_DIS_OP(enable) \
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SPI_MEM_OP(SPI_MEM_OP_CMD((enable) ? 0x06 : 0x04, 1), \
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SPI_MEM_OP_NO_ADDR, \
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SPI_MEM_OP_NO_DUMMY, \
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SPI_MEM_OP_NO_DATA)
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#define SPINAND_READID_OP(ndummy, buf, len) \
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SPI_MEM_OP(SPI_MEM_OP_CMD(0x9f, 1), \
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SPI_MEM_OP_NO_ADDR, \
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SPI_MEM_OP_DUMMY(ndummy, 1), \
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SPI_MEM_OP_DATA_IN(len, buf, 1))
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#define SPINAND_SET_FEATURE_OP(reg, valptr) \
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SPI_MEM_OP(SPI_MEM_OP_CMD(0x1f, 1), \
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SPI_MEM_OP_ADDR(1, reg, 1), \
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SPI_MEM_OP_NO_DUMMY, \
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SPI_MEM_OP_DATA_OUT(1, valptr, 1))
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#define SPINAND_GET_FEATURE_OP(reg, valptr) \
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SPI_MEM_OP(SPI_MEM_OP_CMD(0x0f, 1), \
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SPI_MEM_OP_ADDR(1, reg, 1), \
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SPI_MEM_OP_NO_DUMMY, \
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SPI_MEM_OP_DATA_IN(1, valptr, 1))
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#define SPINAND_BLK_ERASE_OP(addr) \
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SPI_MEM_OP(SPI_MEM_OP_CMD(0xd8, 1), \
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SPI_MEM_OP_ADDR(3, addr, 1), \
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SPI_MEM_OP_NO_DUMMY, \
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SPI_MEM_OP_NO_DATA)
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#define SPINAND_PAGE_READ_OP(addr) \
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SPI_MEM_OP(SPI_MEM_OP_CMD(0x13, 1), \
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SPI_MEM_OP_ADDR(3, addr, 1), \
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SPI_MEM_OP_NO_DUMMY, \
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SPI_MEM_OP_NO_DATA)
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#define SPINAND_PAGE_READ_FROM_CACHE_OP(fast, addr, ndummy, buf, len) \
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SPI_MEM_OP(SPI_MEM_OP_CMD(fast ? 0x0b : 0x03, 1), \
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SPI_MEM_OP_ADDR(2, addr, 1), \
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SPI_MEM_OP_DUMMY(ndummy, 1), \
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SPI_MEM_OP_DATA_IN(len, buf, 1))
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#define SPINAND_PAGE_READ_FROM_CACHE_X2_OP(addr, ndummy, buf, len) \
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SPI_MEM_OP(SPI_MEM_OP_CMD(0x3b, 1), \
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SPI_MEM_OP_ADDR(2, addr, 1), \
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SPI_MEM_OP_DUMMY(ndummy, 1), \
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SPI_MEM_OP_DATA_IN(len, buf, 2))
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#define SPINAND_PAGE_READ_FROM_CACHE_X4_OP(addr, ndummy, buf, len) \
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SPI_MEM_OP(SPI_MEM_OP_CMD(0x6b, 1), \
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SPI_MEM_OP_ADDR(2, addr, 1), \
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SPI_MEM_OP_DUMMY(ndummy, 1), \
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SPI_MEM_OP_DATA_IN(len, buf, 4))
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#define SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(addr, ndummy, buf, len) \
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SPI_MEM_OP(SPI_MEM_OP_CMD(0xbb, 1), \
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SPI_MEM_OP_ADDR(2, addr, 2), \
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SPI_MEM_OP_DUMMY(ndummy, 2), \
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SPI_MEM_OP_DATA_IN(len, buf, 2))
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#define SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(addr, ndummy, buf, len) \
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SPI_MEM_OP(SPI_MEM_OP_CMD(0xeb, 1), \
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SPI_MEM_OP_ADDR(2, addr, 4), \
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SPI_MEM_OP_DUMMY(ndummy, 4), \
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SPI_MEM_OP_DATA_IN(len, buf, 4))
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#define SPINAND_PROG_EXEC_OP(addr) \
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SPI_MEM_OP(SPI_MEM_OP_CMD(0x10, 1), \
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SPI_MEM_OP_ADDR(3, addr, 1), \
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SPI_MEM_OP_NO_DUMMY, \
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SPI_MEM_OP_NO_DATA)
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#define SPINAND_PROG_LOAD(reset, addr, buf, len) \
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SPI_MEM_OP(SPI_MEM_OP_CMD(reset ? 0x02 : 0x84, 1), \
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SPI_MEM_OP_ADDR(2, addr, 1), \
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SPI_MEM_OP_NO_DUMMY, \
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SPI_MEM_OP_DATA_OUT(len, buf, 1))
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#define SPINAND_PROG_LOAD_X4(reset, addr, buf, len) \
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SPI_MEM_OP(SPI_MEM_OP_CMD(reset ? 0x32 : 0x34, 1), \
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SPI_MEM_OP_ADDR(2, addr, 1), \
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SPI_MEM_OP_NO_DUMMY, \
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SPI_MEM_OP_DATA_OUT(len, buf, 4))
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/**
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* Standard SPI NAND flash commands
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*/
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#define SPINAND_CMD_PROG_LOAD_X4 0x32
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#define SPINAND_CMD_PROG_LOAD_RDM_DATA_X4 0x34
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/* feature register */
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#define REG_BLOCK_LOCK 0xa0
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#define BL_ALL_UNLOCKED 0x00
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/* configuration register */
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#define REG_CFG 0xb0
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#define CFG_OTP_ENABLE BIT(6)
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#define CFG_ECC_ENABLE BIT(4)
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#define CFG_QUAD_ENABLE BIT(0)
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/* status register */
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#define REG_STATUS 0xc0
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#define STATUS_BUSY BIT(0)
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#define STATUS_ERASE_FAILED BIT(2)
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#define STATUS_PROG_FAILED BIT(3)
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#define STATUS_ECC_MASK GENMASK(5, 4)
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#define STATUS_ECC_NO_BITFLIPS (0 << 4)
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#define STATUS_ECC_HAS_BITFLIPS (1 << 4)
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#define STATUS_ECC_UNCOR_ERROR (2 << 4)
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struct spinand_op;
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struct spinand_device;
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#define SPINAND_MAX_ID_LEN 4
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/**
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* struct spinand_id - SPI NAND id structure
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* @data: buffer containing the id bytes. Currently 4 bytes large, but can
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* be extended if required
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* @len: ID length
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*
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* struct_spinand_id->data contains all bytes returned after a READ_ID command,
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* including dummy bytes if the chip does not emit ID bytes right after the
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* READ_ID command. The responsibility to extract real ID bytes is left to
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* struct_manufacurer_ops->detect().
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*/
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struct spinand_id {
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u8 data[SPINAND_MAX_ID_LEN];
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int len;
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};
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/**
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* struct manufacurer_ops - SPI NAND manufacturer specific operations
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* @detect: detect a SPI NAND device. Every time a SPI NAND device is probed
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* the core calls the struct_manufacurer_ops->detect() hook of each
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* registered manufacturer until one of them return 1. Note that
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* the first thing to check in this hook is that the manufacturer ID
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* in struct_spinand_device->id matches the manufacturer whose
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* ->detect() hook has been called. Should return 1 if there's a
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* match, 0 if the manufacturer ID does not match and a negative
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* error code otherwise. When true is returned, the core assumes
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* that properties of the NAND chip (spinand->base.memorg and
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* spinand->base.eccreq) have been filled
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* @init: initialize a SPI NAND device
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* @cleanup: cleanup a SPI NAND device
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*
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* Each SPI NAND manufacturer driver should implement this interface so that
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* NAND chips coming from this vendor can be detected and initialized properly.
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*/
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struct spinand_manufacturer_ops {
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int (*detect)(struct spinand_device *spinand);
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int (*init)(struct spinand_device *spinand);
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void (*cleanup)(struct spinand_device *spinand);
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};
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/**
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* struct spinand_manufacturer - SPI NAND manufacturer instance
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* @id: manufacturer ID
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* @name: manufacturer name
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* @ops: manufacturer operations
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*/
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struct spinand_manufacturer {
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u8 id;
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char *name;
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const struct spinand_manufacturer_ops *ops;
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};
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/* SPI NAND manufacturers */
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extern const struct spinand_manufacturer gigadevice_spinand_manufacturer;
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extern const struct spinand_manufacturer macronix_spinand_manufacturer;
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extern const struct spinand_manufacturer micron_spinand_manufacturer;
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extern const struct spinand_manufacturer toshiba_spinand_manufacturer;
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extern const struct spinand_manufacturer winbond_spinand_manufacturer;
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/**
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* struct spinand_op_variants - SPI NAND operation variants
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* @ops: the list of variants for a given operation
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* @nops: the number of variants
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*
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* Some operations like read-from-cache/write-to-cache have several variants
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* depending on the number of IO lines you use to transfer data or address
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* cycles. This structure is a way to describe the different variants supported
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* by a chip and let the core pick the best one based on the SPI mem controller
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* capabilities.
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*/
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struct spinand_op_variants {
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const struct spi_mem_op *ops;
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unsigned int nops;
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};
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#define SPINAND_OP_VARIANTS(name, ...) \
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const struct spinand_op_variants name = { \
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.ops = (struct spi_mem_op[]) { __VA_ARGS__ }, \
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.nops = sizeof((struct spi_mem_op[]){ __VA_ARGS__ }) / \
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sizeof(struct spi_mem_op), \
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}
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/**
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* spinand_ecc_info - description of the on-die ECC implemented by a SPI NAND
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* chip
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* @get_status: get the ECC status. Should return a positive number encoding
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* the number of corrected bitflips if correction was possible or
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* -EBADMSG if there are uncorrectable errors. I can also return
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* other negative error codes if the error is not caused by
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* uncorrectable bitflips
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* @ooblayout: the OOB layout used by the on-die ECC implementation
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*/
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struct spinand_ecc_info {
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int (*get_status)(struct spinand_device *spinand, u8 status);
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const struct mtd_ooblayout_ops *ooblayout;
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};
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#define SPINAND_HAS_QE_BIT BIT(0)
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#define SPINAND_HAS_CR_FEAT_BIT BIT(1)
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/**
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* struct spinand_info - Structure used to describe SPI NAND chips
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* @model: model name
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* @devid: device ID
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* @flags: OR-ing of the SPINAND_XXX flags
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* @memorg: memory organization
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* @eccreq: ECC requirements
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* @eccinfo: on-die ECC info
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* @op_variants: operations variants
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* @op_variants.read_cache: variants of the read-cache operation
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* @op_variants.write_cache: variants of the write-cache operation
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* @op_variants.update_cache: variants of the update-cache operation
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* @select_target: function used to select a target/die. Required only for
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* multi-die chips
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*
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* Each SPI NAND manufacturer driver should have a spinand_info table
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* describing all the chips supported by the driver.
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*/
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struct spinand_info {
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const char *model;
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u8 devid;
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u32 flags;
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struct nand_memory_organization memorg;
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struct nand_ecc_req eccreq;
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struct spinand_ecc_info eccinfo;
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struct {
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const struct spinand_op_variants *read_cache;
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const struct spinand_op_variants *write_cache;
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const struct spinand_op_variants *update_cache;
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} op_variants;
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int (*select_target)(struct spinand_device *spinand,
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unsigned int target);
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};
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#define SPINAND_INFO_OP_VARIANTS(__read, __write, __update) \
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{ \
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.read_cache = __read, \
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.write_cache = __write, \
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.update_cache = __update, \
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}
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#define SPINAND_ECCINFO(__ooblayout, __get_status) \
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.eccinfo = { \
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.ooblayout = __ooblayout, \
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.get_status = __get_status, \
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}
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#define SPINAND_SELECT_TARGET(__func) \
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.select_target = __func,
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#define SPINAND_INFO(__model, __id, __memorg, __eccreq, __op_variants, \
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__flags, ...) \
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{ \
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.model = __model, \
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.devid = __id, \
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.memorg = __memorg, \
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.eccreq = __eccreq, \
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.op_variants = __op_variants, \
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.flags = __flags, \
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__VA_ARGS__ \
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}
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/**
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* struct spinand_device - SPI NAND device instance
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* @base: NAND device instance
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* @slave: pointer to the SPI slave object
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* @lock: lock used to serialize accesses to the NAND
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* @id: NAND ID as returned by READ_ID
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* @flags: NAND flags
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* @op_templates: various SPI mem op templates
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* @op_templates.read_cache: read cache op template
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* @op_templates.write_cache: write cache op template
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* @op_templates.update_cache: update cache op template
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* @select_target: select a specific target/die. Usually called before sending
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* a command addressing a page or an eraseblock embedded in
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* this die. Only required if your chip exposes several dies
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* @cur_target: currently selected target/die
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* @eccinfo: on-die ECC information
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* @cfg_cache: config register cache. One entry per die
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* @databuf: bounce buffer for data
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* @oobbuf: bounce buffer for OOB data
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* @scratchbuf: buffer used for everything but page accesses. This is needed
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* because the spi-mem interface explicitly requests that buffers
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* passed in spi_mem_op be DMA-able, so we can't based the bufs on
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* the stack
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* @manufacturer: SPI NAND manufacturer information
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* @priv: manufacturer private data
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*/
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struct spinand_device {
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struct nand_device base;
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#ifndef __UBOOT__
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struct spi_mem *spimem;
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struct mutex lock;
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#else
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struct spi_slave *slave;
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#endif
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struct spinand_id id;
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u32 flags;
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struct {
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const struct spi_mem_op *read_cache;
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const struct spi_mem_op *write_cache;
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const struct spi_mem_op *update_cache;
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} op_templates;
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int (*select_target)(struct spinand_device *spinand,
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unsigned int target);
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unsigned int cur_target;
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struct spinand_ecc_info eccinfo;
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u8 *cfg_cache;
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u8 *databuf;
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u8 *oobbuf;
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u8 *scratchbuf;
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const struct spinand_manufacturer *manufacturer;
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void *priv;
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};
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/**
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* mtd_to_spinand() - Get the SPI NAND device attached to an MTD instance
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* @mtd: MTD instance
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*
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* Return: the SPI NAND device attached to @mtd.
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*/
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static inline struct spinand_device *mtd_to_spinand(struct mtd_info *mtd)
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{
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return container_of(mtd_to_nanddev(mtd), struct spinand_device, base);
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}
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/**
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* spinand_to_mtd() - Get the MTD device embedded in a SPI NAND device
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* @spinand: SPI NAND device
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*
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* Return: the MTD device embedded in @spinand.
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*/
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static inline struct mtd_info *spinand_to_mtd(struct spinand_device *spinand)
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{
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return nanddev_to_mtd(&spinand->base);
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}
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/**
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* nand_to_spinand() - Get the SPI NAND device embedding an NAND object
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* @nand: NAND object
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*
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* Return: the SPI NAND device embedding @nand.
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*/
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static inline struct spinand_device *nand_to_spinand(struct nand_device *nand)
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{
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return container_of(nand, struct spinand_device, base);
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}
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/**
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* spinand_to_nand() - Get the NAND device embedded in a SPI NAND object
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* @spinand: SPI NAND device
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*
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* Return: the NAND device embedded in @spinand.
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*/
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static inline struct nand_device *
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spinand_to_nand(struct spinand_device *spinand)
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{
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return &spinand->base;
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}
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/**
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* spinand_set_of_node - Attach a DT node to a SPI NAND device
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* @spinand: SPI NAND device
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* @np: DT node
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*
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* Attach a DT node to a SPI NAND device.
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*/
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static inline void spinand_set_of_node(struct spinand_device *spinand,
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const struct device_node *np)
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{
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nanddev_set_of_node(&spinand->base, np);
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}
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int spinand_match_and_init(struct spinand_device *dev,
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const struct spinand_info *table,
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unsigned int table_size, u8 devid);
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int spinand_upd_cfg(struct spinand_device *spinand, u8 mask, u8 val);
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int spinand_select_target(struct spinand_device *spinand, unsigned int target);
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#endif /* __LINUX_MTD_SPINAND_H */
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