mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
336 lines
10 KiB
C
336 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2001 Navin Boppuri / Prashant Patel
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* <nboppuri@trinetcommunication.com>,
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* <pmpatel@trinetcommunication.com>
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* Copyright (c) 2001 Gerd Mennchen <Gerd.Mennchen@icn.siemens.de>
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* Copyright (c) 2001 Wolfgang Denk, DENX Software Engineering, <wd@denx.de>.
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*/
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/*
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* MPC8xx CPM SPI interface.
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*
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* Parts of this code are probably not portable and/or specific to
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* the board which I used for the tests. Please send fixes/complaints
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* to wd@denx.de
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*
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*/
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#include <common.h>
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#include <mpc8xx.h>
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#include <asm/cpm_8xx.h>
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#include <linux/ctype.h>
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#include <malloc.h>
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#include <post.h>
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#include <serial.h>
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#define SPI_EEPROM_WREN 0x06
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#define SPI_EEPROM_RDSR 0x05
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#define SPI_EEPROM_READ 0x03
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#define SPI_EEPROM_WRITE 0x02
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/* ---------------------------------------------------------------
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* Offset for initial SPI buffers in DPRAM:
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* We need a 520 byte scratch DPRAM area to use at an early stage.
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* It is used between the two initialization calls (spi_init_f()
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* and spi_init_r()).
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* The value 0xb00 makes it far enough from the start of the data
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* area (as well as from the stack pointer).
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* --------------------------------------------------------------- */
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#ifndef CONFIG_SYS_SPI_INIT_OFFSET
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#define CONFIG_SYS_SPI_INIT_OFFSET 0xB00
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#endif
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#define CPM_SPI_BASE_RX CPM_SPI_BASE
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#define CPM_SPI_BASE_TX (CPM_SPI_BASE + sizeof(cbd_t))
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/* -------------------
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* Function prototypes
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* ------------------- */
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ssize_t spi_xfer(size_t);
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/* -------------------
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* Variables
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* ------------------- */
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#define MAX_BUFFER 0x104
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/* ----------------------------------------------------------------------
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* Initially we place the RX and TX buffers at a fixed location in DPRAM!
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* ---------------------------------------------------------------------- */
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static uchar *rxbuf =
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(uchar *)&((cpm8xx_t *)&((immap_t *)CONFIG_SYS_IMMR)->im_cpm)->cp_dpmem
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[CONFIG_SYS_SPI_INIT_OFFSET];
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static uchar *txbuf =
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(uchar *)&((cpm8xx_t *)&((immap_t *)CONFIG_SYS_IMMR)->im_cpm)->cp_dpmem
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[CONFIG_SYS_SPI_INIT_OFFSET+MAX_BUFFER];
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/* **************************************************************************
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*
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* Function: spi_init_f
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*
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* Description: Init SPI-Controller (ROM part)
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*
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* return: ---
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*
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* *********************************************************************** */
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void spi_init_f(void)
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{
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immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
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cpm8xx_t __iomem *cp = &immr->im_cpm;
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spi_t __iomem *spi = (spi_t __iomem *)&cp->cp_dparam[PROFF_SPI];
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cbd_t __iomem *tbdf, *rbdf;
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/* Disable relocation */
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out_be16(&spi->spi_rpbase, 0);
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/* 1 */
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/* ------------------------------------------------
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* Initialize Port B SPI pins -> page 34-8 MPC860UM
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* (we are only in Master Mode !)
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* ------------------------------------------------ */
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/* --------------------------------------------
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* GPIO or per. Function
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* PBPAR[28] = 1 [0x00000008] -> PERI: (SPIMISO)
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* PBPAR[29] = 1 [0x00000004] -> PERI: (SPIMOSI)
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* PBPAR[30] = 1 [0x00000002] -> PERI: (SPICLK)
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* PBPAR[31] = 0 [0x00000001] -> GPIO: (CS for PCUE/CCM-EEPROM)
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* -------------------------------------------- */
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clrsetbits_be32(&cp->cp_pbpar, 0x00000001, 0x0000000E); /* set bits */
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/* ----------------------------------------------
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* In/Out or per. Function 0/1
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* PBDIR[28] = 1 [0x00000008] -> PERI1: SPIMISO
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* PBDIR[29] = 1 [0x00000004] -> PERI1: SPIMOSI
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* PBDIR[30] = 1 [0x00000002] -> PERI1: SPICLK
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* PBDIR[31] = 1 [0x00000001] -> GPIO OUT: CS for PCUE/CCM-EEPROM
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* ---------------------------------------------- */
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setbits_be32(&cp->cp_pbdir, 0x0000000F);
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/* ----------------------------------------------
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* open drain or active output
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* PBODR[28] = 1 [0x00000008] -> open drain: SPIMISO
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* PBODR[29] = 0 [0x00000004] -> active output SPIMOSI
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* PBODR[30] = 0 [0x00000002] -> active output: SPICLK
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* PBODR[31] = 0 [0x00000001] -> active output GPIO OUT: CS for PCUE/CCM
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* ---------------------------------------------- */
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clrsetbits_be16(&cp->cp_pbodr, 0x00000007, 0x00000008);
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/* Initialize the parameter ram.
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* We need to make sure many things are initialized to zero
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*/
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out_be32(&spi->spi_rstate, 0);
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out_be32(&spi->spi_rdp, 0);
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out_be16(&spi->spi_rbptr, 0);
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out_be16(&spi->spi_rbc, 0);
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out_be32(&spi->spi_rxtmp, 0);
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out_be32(&spi->spi_tstate, 0);
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out_be32(&spi->spi_tdp, 0);
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out_be16(&spi->spi_tbptr, 0);
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out_be16(&spi->spi_tbc, 0);
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out_be32(&spi->spi_txtmp, 0);
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/* 3 */
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/* Set up the SPI parameters in the parameter ram */
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out_be16(&spi->spi_rbase, CPM_SPI_BASE_RX);
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out_be16(&spi->spi_tbase, CPM_SPI_BASE_TX);
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/***********IMPORTANT******************/
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/*
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* Setting transmit and receive buffer descriptor pointers
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* initially to rbase and tbase. Only the microcode patches
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* documentation talks about initializing this pointer. This
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* is missing from the sample I2C driver. If you dont
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* initialize these pointers, the kernel hangs.
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*/
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out_be16(&spi->spi_rbptr, CPM_SPI_BASE_RX);
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out_be16(&spi->spi_tbptr, CPM_SPI_BASE_TX);
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/* 4 */
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/* Init SPI Tx + Rx Parameters */
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while (in_be16(&cp->cp_cpcr) & CPM_CR_FLG)
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;
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out_be16(&cp->cp_cpcr, mk_cr_cmd(CPM_CR_CH_SPI, CPM_CR_INIT_TRX) |
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CPM_CR_FLG);
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while (in_be16(&cp->cp_cpcr) & CPM_CR_FLG)
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;
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/* 5 */
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/* Set SDMA configuration register */
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out_be32(&immr->im_siu_conf.sc_sdcr, 0x0001);
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/* 6 */
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/* Set to big endian. */
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out_8(&spi->spi_tfcr, SMC_EB);
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out_8(&spi->spi_rfcr, SMC_EB);
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/* 7 */
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/* Set maximum receive size. */
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out_be16(&spi->spi_mrblr, MAX_BUFFER);
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/* 8 + 9 */
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/* tx and rx buffer descriptors */
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tbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_TX];
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rbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_RX];
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clrbits_be16(&tbdf->cbd_sc, BD_SC_READY);
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clrbits_be16(&rbdf->cbd_sc, BD_SC_EMPTY);
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/* Set the bd's rx and tx buffer address pointers */
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out_be32(&rbdf->cbd_bufaddr, (ulong)rxbuf);
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out_be32(&tbdf->cbd_bufaddr, (ulong)txbuf);
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/* 10 + 11 */
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out_8(&cp->cp_spim, 0); /* Mask all SPI events */
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out_8(&cp->cp_spie, SPI_EMASK); /* Clear all SPI events */
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return;
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}
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/* **************************************************************************
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*
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* Function: spi_init_r
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*
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* Description: Init SPI-Controller (RAM part) -
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* The malloc engine is ready and we can move our buffers to
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* normal RAM
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*
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* return: ---
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*
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* *********************************************************************** */
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void spi_init_r(void)
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{
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immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
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cpm8xx_t __iomem *cp = &immr->im_cpm;
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spi_t __iomem *spi = (spi_t __iomem *)&cp->cp_dparam[PROFF_SPI];
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cbd_t __iomem *tbdf, *rbdf;
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/* Disable relocation */
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out_be16(&spi->spi_rpbase, 0);
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/* tx and rx buffer descriptors */
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tbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_TX];
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rbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_RX];
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/* Allocate memory for RX and TX buffers */
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rxbuf = (uchar *)malloc(MAX_BUFFER);
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txbuf = (uchar *)malloc(MAX_BUFFER);
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out_be32(&rbdf->cbd_bufaddr, (ulong)rxbuf);
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out_be32(&tbdf->cbd_bufaddr, (ulong)txbuf);
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return;
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}
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/****************************************************************************
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* Function: spi_write
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**************************************************************************** */
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ssize_t spi_write(uchar *addr, int alen, uchar *buffer, int len)
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{
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int i;
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memset(rxbuf, 0, MAX_BUFFER);
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memset(txbuf, 0, MAX_BUFFER);
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*txbuf = SPI_EEPROM_WREN; /* write enable */
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spi_xfer(1);
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memcpy(txbuf, addr, alen);
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*txbuf = SPI_EEPROM_WRITE; /* WRITE memory array */
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memcpy(alen + txbuf, buffer, len);
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spi_xfer(alen + len);
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/* ignore received data */
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for (i = 0; i < 1000; i++) {
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*txbuf = SPI_EEPROM_RDSR; /* read status */
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txbuf[1] = 0;
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spi_xfer(2);
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if (!(rxbuf[1] & 1))
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break;
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udelay(1000);
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}
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if (i >= 1000)
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printf("*** spi_write: Time out while writing!\n");
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return len;
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}
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/****************************************************************************
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* Function: spi_read
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**************************************************************************** */
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ssize_t spi_read(uchar *addr, int alen, uchar *buffer, int len)
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{
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memset(rxbuf, 0, MAX_BUFFER);
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memset(txbuf, 0, MAX_BUFFER);
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memcpy(txbuf, addr, alen);
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*txbuf = SPI_EEPROM_READ; /* READ memory array */
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/*
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* There is a bug in 860T (?) that cuts the last byte of input
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* if we're reading into DPRAM. The solution we choose here is
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* to always read len+1 bytes (we have one extra byte at the
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* end of the buffer).
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*/
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spi_xfer(alen + len + 1);
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memcpy(buffer, alen + rxbuf, len);
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return len;
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}
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/****************************************************************************
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* Function: spi_xfer
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**************************************************************************** */
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ssize_t spi_xfer(size_t count)
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{
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immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
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cpm8xx_t __iomem *cp = &immr->im_cpm;
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spi_t __iomem *spi = (spi_t __iomem *)&cp->cp_dparam[PROFF_SPI];
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cbd_t __iomem *tbdf, *rbdf;
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int tm;
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/* Disable relocation */
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out_be16(&spi->spi_rpbase, 0);
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tbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_TX];
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rbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_RX];
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/* Set CS for device */
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clrbits_be32(&cp->cp_pbdat, 0x0001);
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/* Setting tx bd status and data length */
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out_be16(&tbdf->cbd_sc, BD_SC_READY | BD_SC_LAST | BD_SC_WRAP);
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out_be16(&tbdf->cbd_datlen, count);
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/* Setting rx bd status and data length */
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out_be16(&rbdf->cbd_sc, BD_SC_EMPTY | BD_SC_WRAP);
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out_be16(&rbdf->cbd_datlen, 0); /* rx length has no significance */
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clrsetbits_be16(&cp->cp_spmode, ~SPMODE_LOOP, SPMODE_REV | SPMODE_MSTR |
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SPMODE_EN | SPMODE_LEN(8) | SPMODE_PM(0x8));
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out_8(&cp->cp_spim, 0); /* Mask all SPI events */
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out_8(&cp->cp_spie, SPI_EMASK); /* Clear all SPI events */
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/* start spi transfer */
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setbits_8(&cp->cp_spcom, SPI_STR); /* Start transmit */
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/* --------------------------------
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* Wait for SPI transmit to get out
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* or time out (1 second = 1000 ms)
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* -------------------------------- */
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for (tm = 0; tm < 1000; ++tm) {
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if (in_8(&cp->cp_spie) & SPI_TXB) /* Tx Buffer Empty */
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break;
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if ((in_be16(&tbdf->cbd_sc) & BD_SC_READY) == 0)
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break;
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udelay(1000);
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}
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if (tm >= 1000)
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printf("*** spi_xfer: Time out while xferring to/from SPI!\n");
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/* Clear CS for device */
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setbits_be32(&cp->cp_pbdat, 0x0001);
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return count;
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}
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