mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-10-04 18:40:42 +09:00
c9e1f58818
In the previous patches, we introduced the SPL/TPL fraamework. For SD/SPI flash booting way, we introduce the SPL to enable a loader stub. The SPL was loaded by the code from the internal on-chip ROM. The SPL initializes the DDR according to the SPD and loads the final uboot image into DDR, then jump to the DDR to begin execution. For NAND booting way, the nand SPL has size limitation on some board(e.g. P1010RDB), it can not be more than 8KB, we can call it "minimal SPL", So the dynamic DDR driver doesn't fit into this minimum SPL. We added the TPL that is loaded by the the minimal SPL. The TPL initializes the DDR according to the SPD and loads the final uboot image into DDR,then jump to the DDR to begin execution. This patch enabled SPL/TPL for P1010RDB to support starting from NAND/SD/SPI flash with SPL framework and initializing the DDR according to SPD in the SPL/TPL. Because the minimal SPL load the TPL to L2 SRAM and the jump to the L2 SRAM to execute, so the section .resetvec is no longer needed. Signed-off-by: Ying Zhang <b40530@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
109 lines
2.5 KiB
C
109 lines
2.5 KiB
C
/* Copyright 2013 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <ns16550.h>
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#include <malloc.h>
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#include <mmc.h>
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#include <nand.h>
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#include <i2c.h>
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#include <fsl_esdhc.h>
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#include <spi_flash.h>
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DECLARE_GLOBAL_DATA_PTR;
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ulong get_effective_memsize(void)
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{
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return CONFIG_SYS_L2_SIZE;
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}
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void board_init_f(ulong bootflag)
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{
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u32 plat_ratio;
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ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
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struct fsl_ifc *ifc = (void *)CONFIG_SYS_IFC_ADDR;
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console_init_f();
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/* Clock configuration to access CPLD using IFC(GPCM) */
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setbits_be32(&ifc->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
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#ifdef CONFIG_P1010RDB_PB
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setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS);
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#endif
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/* initialize selected port with appropriate baud rate */
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plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
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plat_ratio >>= 1;
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gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
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NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
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gd->bus_clk / 16 / CONFIG_BAUDRATE);
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#ifdef CONFIG_SPL_MMC_BOOT
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puts("\nSD boot...\n");
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#elif defined(CONFIG_SPL_SPI_BOOT)
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puts("\nSPI Flash boot...\n");
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#endif
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/* copy code to RAM and jump to it - this should not return */
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/* NOTE - code has to be copied out of NAND buffer before
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* other blocks can be read.
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*/
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relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
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}
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void board_init_r(gd_t *gd, ulong dest_addr)
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{
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/* Pointer is writable since we allocated a register for it */
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gd = (gd_t *)CONFIG_SPL_GD_ADDR;
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bd_t *bd;
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memset(gd, 0, sizeof(gd_t));
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bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
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memset(bd, 0, sizeof(bd_t));
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gd->bd = bd;
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bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
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bd->bi_memsize = CONFIG_SYS_L2_SIZE;
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probecpu();
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get_clocks();
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mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
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CONFIG_SPL_RELOC_MALLOC_SIZE);
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#ifndef CONFIG_SPL_NAND_BOOT
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env_init();
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#endif
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#ifdef CONFIG_SPL_MMC_BOOT
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mmc_initialize(bd);
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#endif
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/* relocate environment function pointers etc. */
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#ifdef CONFIG_SPL_NAND_BOOT
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nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
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(uchar *)CONFIG_ENV_ADDR);
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gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
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gd->env_valid = 1;
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#else
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env_relocate();
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#endif
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i2c_init_all();
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gd->ram_size = initdram(0);
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#ifdef CONFIG_SPL_NAND_BOOT
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puts("\nTertiary program loader running in sram...");
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#else
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puts("\nSecond program loader running in sram...");
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#endif
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#ifdef CONFIG_SPL_MMC_BOOT
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mmc_boot();
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#elif defined(CONFIG_SPL_SPI_BOOT)
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spi_boot();
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#elif defined(CONFIG_SPL_NAND_BOOT)
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nand_boot();
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#endif
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}
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