mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-16 23:18:51 +09:00
![Vignesh R](/assets/img/avatar_default.png)
Now that new SPI NOR layer uses stateless 4 byte opcodes by default, don't enable SPI_FLASH_BAR. For SPI controllers that cannot support 4-byte addressing, (stm32_qspi.c, fsl_qspi.c, mtk_qspi.c, ich.c, renesas_rpc_spi.c) add an imply clause to enable SPI_FLASH_BAR so as to not break functionality. Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
60 lines
1.5 KiB
Plaintext
60 lines
1.5 KiB
Plaintext
CONFIG_ARM=y
|
|
CONFIG_ARCH_SOCFPGA=y
|
|
CONFIG_SYS_TEXT_BASE=0x01000040
|
|
CONFIG_SYS_MALLOC_F_LEN=0x2000
|
|
CONFIG_TARGET_SOCFPGA_IS1=y
|
|
CONFIG_SPL=y
|
|
CONFIG_SPL_STACK_R_ADDR=0x00800000
|
|
CONFIG_DISTRO_DEFAULTS=y
|
|
CONFIG_NR_DRAM_BANKS=1
|
|
CONFIG_FIT=y
|
|
CONFIG_USE_BOOTARGS=y
|
|
CONFIG_BOOTARGS="console=ttyS0,115200"
|
|
# CONFIG_USE_BOOTCOMMAND is not set
|
|
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
|
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
|
|
CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
|
|
CONFIG_VERSION_VARIABLE=y
|
|
# CONFIG_DISPLAY_BOARDINFO is not set
|
|
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
|
CONFIG_SPL_STACK_R=y
|
|
CONFIG_SPL_SPI_LOAD=y
|
|
CONFIG_CMD_ASKENV=y
|
|
CONFIG_CMD_GREPENV=y
|
|
# CONFIG_CMD_FLASH is not set
|
|
CONFIG_CMD_GPIO=y
|
|
CONFIG_CMD_I2C=y
|
|
CONFIG_CMD_SF=y
|
|
CONFIG_CMD_SPI=y
|
|
CONFIG_CMD_CACHE=y
|
|
CONFIG_CMD_TIME=y
|
|
CONFIG_CMD_EXT4_WRITE=y
|
|
CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
|
|
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)0"
|
|
CONFIG_CMD_UBI=y
|
|
# CONFIG_ISO_PARTITION is not set
|
|
# CONFIG_EFI_PARTITION is not set
|
|
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_is1"
|
|
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
|
CONFIG_SPL_DM=y
|
|
CONFIG_SPL_DM_SEQ_ALIAS=y
|
|
CONFIG_BOOTCOUNT_LIMIT=y
|
|
CONFIG_SYS_BOOTCOUNT_ADDR=0xfffffff8
|
|
CONFIG_FPGA_SOCFPGA=y
|
|
CONFIG_DM_GPIO=y
|
|
CONFIG_DWAPB_GPIO=y
|
|
CONFIG_DM_I2C=y
|
|
CONFIG_SYS_I2C_DW=y
|
|
# CONFIG_MMC is not set
|
|
CONFIG_MTD_DEVICE=y
|
|
CONFIG_SPI_FLASH=y
|
|
CONFIG_SPI_FLASH_STMICRO=y
|
|
CONFIG_PHY_MICREL=y
|
|
CONFIG_PHY_MICREL_KSZ90X1=y
|
|
CONFIG_DM_ETH=y
|
|
CONFIG_ETH_DESIGNWARE=y
|
|
CONFIG_MII=y
|
|
CONFIG_DM_RESET=y
|
|
CONFIG_SPI=y
|
|
CONFIG_CADENCE_QSPI=y
|