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https://github.com/brain-hackers/u-boot-brain
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![Hannes Petermaier](/assets/img/avatar_default.png)
B&R boards are using Phy Addresses 'one' and 'two', prior this was defined through #define PHYADDR 1 within a header file. Now this is addresses are given with device-driver structure. Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
217 lines
5.4 KiB
C
217 lines
5.4 KiB
C
/*
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* common.c
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*
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* common board functions for B&R boards
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*
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* Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at>
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* Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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*/
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#include <common.h>
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#include <errno.h>
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#include <spl.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/omap.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include <i2c.h>
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#include <miiphy.h>
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#include <cpsw.h>
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#include <power/tps65217.h>
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#include "bur_common.h"
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static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
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/* --------------------------------------------------------------------------*/
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void blink(u32 blinks, u32 intervall, u32 pin)
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{
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gpio_direction_output(pin, 0);
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int val = 0;
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do {
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val ^= 0x01;
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gpio_set_value(pin, val);
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mdelay(intervall);
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} while (blinks--);
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gpio_set_value(pin, 0);
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}
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#ifdef CONFIG_SPL_BUILD
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void pmicsetup(u32 mpupll)
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{
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int mpu_vdd;
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int usb_cur_lim;
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/* setup I2C */
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enable_i2c0_pin_mux();
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i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
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if (i2c_probe(TPS65217_CHIP_PM)) {
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puts("PMIC (0x24) not found! skip further initalization.\n");
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return;
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}
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/* Get the frequency which is defined by device fuses */
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dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
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printf("detected max. frequency: %d - ", dpll_mpu_opp100.m);
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if (0 != mpupll) {
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dpll_mpu_opp100.m = MPUPLL_M_1000;
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printf("retuning MPU-PLL to: %d MHz.\n", dpll_mpu_opp100.m);
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} else {
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puts("ok.\n");
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}
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/*
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* Increase USB current limit to 1300mA or 1800mA and set
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* the MPU voltage controller as needed.
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*/
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if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
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usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
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mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
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} else {
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usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
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mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
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}
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if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_POWER_PATH,
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usb_cur_lim, TPS65217_USB_INPUT_CUR_LIMIT_MASK))
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puts("tps65217_reg_write failure\n");
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/* Set DCDC3 (CORE) voltage to 1.125V */
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if (tps65217_voltage_update(TPS65217_DEFDCDC3,
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TPS65217_DCDC_VOLT_SEL_1125MV)) {
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puts("tps65217_voltage_update failure\n");
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return;
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}
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/* Set CORE Frequencies to OPP100 */
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do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
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/* Set DCDC2 (MPU) voltage */
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if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
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puts("tps65217_voltage_update failure\n");
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return;
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}
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/* Set LDO3 to 1.8V */
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if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
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TPS65217_DEFLS1,
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TPS65217_LDO_VOLTAGE_OUT_1_8,
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TPS65217_LDO_MASK))
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puts("tps65217_reg_write failure\n");
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/* Set LDO4 to 3.3V */
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if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
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TPS65217_DEFLS2,
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TPS65217_LDO_VOLTAGE_OUT_3_3,
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TPS65217_LDO_MASK))
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puts("tps65217_reg_write failure\n");
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/* Set MPU Frequency to what we detected now that voltages are set */
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do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
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}
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void set_uart_mux_conf(void)
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{
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enable_uart0_pin_mux();
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}
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void set_mux_conf_regs(void)
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{
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enable_board_pin_mux();
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}
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#endif /* CONFIG_SPL_BUILD */
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#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
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(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
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static void cpsw_control(int enabled)
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{
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/* VTP can be added here */
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return;
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}
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/* describing port offsets of TI's CPSW block */
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static struct cpsw_slave_data cpsw_slaves[] = {
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{
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.slave_reg_ofs = 0x208,
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.sliver_reg_ofs = 0xd80,
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.phy_addr = 1,
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},
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{
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.slave_reg_ofs = 0x308,
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.sliver_reg_ofs = 0xdc0,
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.phy_addr = 2,
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},
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};
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static struct cpsw_platform_data cpsw_data = {
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.mdio_base = CPSW_MDIO_BASE,
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.cpsw_base = CPSW_BASE,
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.mdio_div = 0xff,
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.channels = 8,
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.cpdma_reg_ofs = 0x800,
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.slaves = 1,
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.slave_data = cpsw_slaves,
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.ale_reg_ofs = 0xd00,
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.ale_entries = 1024,
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.host_port_reg_ofs = 0x108,
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.hw_stats_reg_ofs = 0x900,
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.bd_ram_ofs = 0x2000,
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.mac_control = (1 << 5),
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.control = cpsw_control,
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.host_port_num = 0,
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.version = CPSW_CTRL_VERSION_2,
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};
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#endif /* CONFIG_DRIVER_TI_CPSW, ... */
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#if defined(CONFIG_DRIVER_TI_CPSW)
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int board_eth_init(bd_t *bis)
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{
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int rv = 0;
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uint8_t mac_addr[6];
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uint32_t mac_hi, mac_lo;
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/* try reading mac address from efuse */
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mac_lo = readl(&cdev->macid0l);
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mac_hi = readl(&cdev->macid0h);
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mac_addr[0] = mac_hi & 0xFF;
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mac_addr[1] = (mac_hi & 0xFF00) >> 8;
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mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
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mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
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mac_addr[4] = mac_lo & 0xFF;
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mac_addr[5] = (mac_lo & 0xFF00) >> 8;
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#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
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(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
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if (!getenv("ethaddr")) {
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printf("<ethaddr> not set. Validating first E-fuse MAC ... ");
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if (is_valid_ether_addr(mac_addr)) {
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printf("using: %02X:%02X:%02X:%02X:%02X:%02X.\n",
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mac_addr[0], mac_addr[1], mac_addr[2],
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mac_addr[3], mac_addr[4], mac_addr[5]
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);
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eth_setenv_enetaddr("ethaddr", mac_addr);
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}
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}
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writel(MII_MODE_ENABLE, &cdev->miisel);
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cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_MII;
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cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_MII;
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rv = cpsw_register(&cpsw_data);
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if (rv < 0) {
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printf("Error %d registering CPSW switch\n", rv);
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return 0;
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}
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#endif /* CONFIG_DRIVER_TI_CPSW, ... */
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return rv;
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}
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#endif /* CONFIG_DRIVER_TI_CPSW */
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