mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-05 02:36:39 +09:00
573a3811ed
If the system is running PSCI firmware, the System Reset function (func ID: 0x80000009) is supposed to be handled by PSCI, that is, the SoC/board specific reset implementation should be moved to PSCI. U-Boot should call the PSCI service according to the arm-smccc manner. The arm-smccc is supported on ARMv7 or later. Especially, ARMv8 generation SoCs are likely to run ARM Trusted Firmware BL31. In this case, U-Boot is a non-secure world boot loader, so it should not be able to reset the system directly. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
104 lines
3.4 KiB
C
104 lines
3.4 KiB
C
/*
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* ARM Power State and Coordination Interface (PSCI) header
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*
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* This header holds common PSCI defines and macros shared
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* by: ARM kernel, ARM64 kernel, KVM ARM/ARM64 and user space.
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*
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* Copyright (C) 2014 Linaro Ltd.
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* Author: Anup Patel <anup.patel@linaro.org>
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*/
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#ifndef _UAPI_LINUX_PSCI_H
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#define _UAPI_LINUX_PSCI_H
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/*
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* PSCI v0.1 interface
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*
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* The PSCI v0.1 function numbers are implementation defined.
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*
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* Only PSCI return values such as: SUCCESS, NOT_SUPPORTED,
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* INVALID_PARAMS, and DENIED defined below are applicable
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* to PSCI v0.1.
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*/
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/* PSCI v0.2 interface */
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#define PSCI_0_2_FN_BASE 0x84000000
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#define PSCI_0_2_FN(n) (PSCI_0_2_FN_BASE + (n))
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#define PSCI_0_2_64BIT 0x40000000
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#define PSCI_0_2_FN64_BASE \
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(PSCI_0_2_FN_BASE + PSCI_0_2_64BIT)
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#define PSCI_0_2_FN64(n) (PSCI_0_2_FN64_BASE + (n))
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#define PSCI_0_2_FN_PSCI_VERSION PSCI_0_2_FN(0)
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#define PSCI_0_2_FN_CPU_SUSPEND PSCI_0_2_FN(1)
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#define PSCI_0_2_FN_CPU_OFF PSCI_0_2_FN(2)
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#define PSCI_0_2_FN_CPU_ON PSCI_0_2_FN(3)
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#define PSCI_0_2_FN_AFFINITY_INFO PSCI_0_2_FN(4)
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#define PSCI_0_2_FN_MIGRATE PSCI_0_2_FN(5)
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#define PSCI_0_2_FN_MIGRATE_INFO_TYPE PSCI_0_2_FN(6)
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#define PSCI_0_2_FN_MIGRATE_INFO_UP_CPU PSCI_0_2_FN(7)
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#define PSCI_0_2_FN_SYSTEM_OFF PSCI_0_2_FN(8)
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#define PSCI_0_2_FN_SYSTEM_RESET PSCI_0_2_FN(9)
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#define PSCI_0_2_FN64_CPU_SUSPEND PSCI_0_2_FN64(1)
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#define PSCI_0_2_FN64_CPU_ON PSCI_0_2_FN64(3)
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#define PSCI_0_2_FN64_AFFINITY_INFO PSCI_0_2_FN64(4)
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#define PSCI_0_2_FN64_MIGRATE PSCI_0_2_FN64(5)
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#define PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU PSCI_0_2_FN64(7)
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/* PSCI v0.2 power state encoding for CPU_SUSPEND function */
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#define PSCI_0_2_POWER_STATE_ID_MASK 0xffff
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#define PSCI_0_2_POWER_STATE_ID_SHIFT 0
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#define PSCI_0_2_POWER_STATE_TYPE_SHIFT 16
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#define PSCI_0_2_POWER_STATE_TYPE_MASK \
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(0x1 << PSCI_0_2_POWER_STATE_TYPE_SHIFT)
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#define PSCI_0_2_POWER_STATE_AFFL_SHIFT 24
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#define PSCI_0_2_POWER_STATE_AFFL_MASK \
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(0x3 << PSCI_0_2_POWER_STATE_AFFL_SHIFT)
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/* PSCI v0.2 affinity level state returned by AFFINITY_INFO */
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#define PSCI_0_2_AFFINITY_LEVEL_ON 0
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#define PSCI_0_2_AFFINITY_LEVEL_OFF 1
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#define PSCI_0_2_AFFINITY_LEVEL_ON_PENDING 2
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/* PSCI v0.2 multicore support in Trusted OS returned by MIGRATE_INFO_TYPE */
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#define PSCI_0_2_TOS_UP_MIGRATE 0
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#define PSCI_0_2_TOS_UP_NO_MIGRATE 1
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#define PSCI_0_2_TOS_MP 2
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/* PSCI version decoding (independent of PSCI version) */
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#define PSCI_VERSION_MAJOR_SHIFT 16
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#define PSCI_VERSION_MINOR_MASK \
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((1U << PSCI_VERSION_MAJOR_SHIFT) - 1)
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#define PSCI_VERSION_MAJOR_MASK ~PSCI_VERSION_MINOR_MASK
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#define PSCI_VERSION_MAJOR(ver) \
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(((ver) & PSCI_VERSION_MAJOR_MASK) >> PSCI_VERSION_MAJOR_SHIFT)
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#define PSCI_VERSION_MINOR(ver) \
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((ver) & PSCI_VERSION_MINOR_MASK)
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/* PSCI return values (inclusive of all PSCI versions) */
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#define PSCI_RET_SUCCESS 0
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#define PSCI_RET_NOT_SUPPORTED -1
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#define PSCI_RET_INVALID_PARAMS -2
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#define PSCI_RET_DENIED -3
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#define PSCI_RET_ALREADY_ON -4
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#define PSCI_RET_ON_PENDING -5
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#define PSCI_RET_INTERNAL_FAILURE -6
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#define PSCI_RET_NOT_PRESENT -7
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#define PSCI_RET_DISABLED -8
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#ifdef CONFIG_ARM_PSCI_FW
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typedef unsigned long (psci_fn)(unsigned long, unsigned long,
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unsigned long, unsigned long);
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extern psci_fn *invoke_psci_fn;
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#else
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unsigned long invoke_psci_fn(unsigned long a0, unsigned long a1,
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unsigned long a2, unsigned long a3)
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{
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return PSCI_RET_DISABLED;
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}
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#endif
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#endif /* _UAPI_LINUX_PSCI_H */
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