mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-17 23:48:52 +09:00
520c174b35
Despite the comment in the code, CSC unit is never used. According to the only public description of DW HDMI controller (i.MX6 manual), CSC unit is bypassed in MC_FLOWCTRL register and then actually powered down in MC_CLKDIS register. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Simon Glass <sjg@chromium.org>
896 lines
23 KiB
C
896 lines
23 KiB
C
/*
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* Copyright (c) 2015 Google, Inc
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* Copyright 2014 Rockchip Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <clk.h>
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#include <display.h>
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#include <dm.h>
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#include <edid.h>
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#include <regmap.h>
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#include <syscon.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/grf_rk3288.h>
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#include <asm/arch/hdmi_rk3288.h>
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#include <power/regulator.h>
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struct tmds_n_cts {
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u32 tmds;
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u32 cts;
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u32 n;
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};
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struct rk_hdmi_priv {
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struct rk3288_hdmi *regs;
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struct rk3288_grf *grf;
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};
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static const struct tmds_n_cts n_cts_table[] = {
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{
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.tmds = 25175000, .n = 6144, .cts = 25175,
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}, {
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.tmds = 25200000, .n = 6144, .cts = 25200,
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}, {
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.tmds = 27000000, .n = 6144, .cts = 27000,
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}, {
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.tmds = 27027000, .n = 6144, .cts = 27027,
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}, {
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.tmds = 40000000, .n = 6144, .cts = 40000,
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}, {
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.tmds = 54000000, .n = 6144, .cts = 54000,
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}, {
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.tmds = 54054000, .n = 6144, .cts = 54054,
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}, {
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.tmds = 65000000, .n = 6144, .cts = 65000,
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}, {
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.tmds = 74176000, .n = 11648, .cts = 140625,
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}, {
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.tmds = 74250000, .n = 6144, .cts = 74250,
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}, {
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.tmds = 83500000, .n = 6144, .cts = 83500,
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}, {
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.tmds = 106500000, .n = 6144, .cts = 106500,
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}, {
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.tmds = 108000000, .n = 6144, .cts = 108000,
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}, {
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.tmds = 148352000, .n = 5824, .cts = 140625,
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}, {
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.tmds = 148500000, .n = 6144, .cts = 148500,
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}, {
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.tmds = 297000000, .n = 5120, .cts = 247500,
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}
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};
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struct hdmi_mpll_config {
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u64 mpixelclock;
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/* Mode of Operation and PLL Dividers Control Register */
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u32 cpce;
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/* PLL Gmp Control Register */
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u32 gmp;
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/* PLL Current COntrol Register */
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u32 curr;
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};
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struct hdmi_phy_config {
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u64 mpixelclock;
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u32 sym_ctr; /* clock symbol and transmitter control */
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u32 term; /* transmission termination value */
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u32 vlev_ctr; /* voltage level control */
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};
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static const struct hdmi_phy_config rockchip_phy_config[] = {
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{
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.mpixelclock = 74250000,
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.sym_ctr = 0x8009, .term = 0x0004, .vlev_ctr = 0x0272,
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}, {
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.mpixelclock = 148500000,
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.sym_ctr = 0x802b, .term = 0x0004, .vlev_ctr = 0x028d,
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}, {
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.mpixelclock = 297000000,
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.sym_ctr = 0x8039, .term = 0x0005, .vlev_ctr = 0x028d,
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}, {
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.mpixelclock = ~0ul,
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.sym_ctr = 0x0000, .term = 0x0000, .vlev_ctr = 0x0000,
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}
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};
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static const struct hdmi_mpll_config rockchip_mpll_cfg[] = {
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{
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.mpixelclock = 40000000,
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.cpce = 0x00b3, .gmp = 0x0000, .curr = 0x0018,
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}, {
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.mpixelclock = 65000000,
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.cpce = 0x0072, .gmp = 0x0001, .curr = 0x0028,
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}, {
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.mpixelclock = 66000000,
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.cpce = 0x013e, .gmp = 0x0003, .curr = 0x0038,
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}, {
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.mpixelclock = 83500000,
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.cpce = 0x0072, .gmp = 0x0001, .curr = 0x0028,
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}, {
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.mpixelclock = 146250000,
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.cpce = 0x0051, .gmp = 0x0002, .curr = 0x0038,
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}, {
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.mpixelclock = 148500000,
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.cpce = 0x0051, .gmp = 0x0003, .curr = 0x0000,
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}, {
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.mpixelclock = ~0ul,
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.cpce = 0x0051, .gmp = 0x0003, .curr = 0x0000,
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}
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};
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static void hdmi_set_clock_regenerator(struct rk3288_hdmi *regs, u32 n, u32 cts)
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{
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uint cts3;
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uint n3;
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/* first set ncts_atomic_write (if present) */
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n3 = HDMI_AUD_N3_NCTS_ATOMIC_WRITE;
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writel(n3, ®s->aud_n3);
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/* set cts_manual (if present) */
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cts3 = HDMI_AUD_CTS3_CTS_MANUAL;
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cts3 |= HDMI_AUD_CTS3_N_SHIFT_1 << HDMI_AUD_CTS3_N_SHIFT_OFFSET;
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cts3 |= (cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK;
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/* write cts values; cts3 must be written first */
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writel(cts3, ®s->aud_cts3);
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writel((cts >> 8) & 0xff, ®s->aud_cts2);
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writel(cts & 0xff, ®s->aud_cts1);
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/* write n values; n1 must be written last */
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n3 |= (n >> 16) & HDMI_AUD_N3_AUDN19_16_MASK;
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writel(n3, ®s->aud_n3);
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writel((n >> 8) & 0xff, ®s->aud_n2);
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writel(n & 0xff, ®s->aud_n1);
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writel(HDMI_AUD_INPUTCLKFS_128, ®s->aud_inputclkfs);
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}
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static int hdmi_lookup_n_cts(u32 pixel_clk)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(n_cts_table); i++)
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if (pixel_clk <= n_cts_table[i].tmds)
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break;
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if (i >= ARRAY_SIZE(n_cts_table))
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return -1;
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return i;
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}
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static void hdmi_audio_set_samplerate(struct rk3288_hdmi *regs, u32 pixel_clk)
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{
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u32 clk_n, clk_cts;
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int index;
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index = hdmi_lookup_n_cts(pixel_clk);
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if (index == -1) {
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debug("audio not supported for pixel clk %d\n", pixel_clk);
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return;
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}
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clk_n = n_cts_table[index].n;
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clk_cts = n_cts_table[index].cts;
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hdmi_set_clock_regenerator(regs, clk_n, clk_cts);
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}
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/*
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* this submodule is responsible for the video data synchronization.
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* for example, for rgb 4:4:4 input, the data map is defined as
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* pin{47~40} <==> r[7:0]
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* pin{31~24} <==> g[7:0]
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* pin{15~8} <==> b[7:0]
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*/
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static void hdmi_video_sample(struct rk3288_hdmi *regs)
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{
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u32 color_format = 0x01;
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uint val;
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val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
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((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
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HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
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writel(val, ®s->tx_invid0);
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/* enable tx stuffing: when de is inactive, fix the output data to 0 */
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val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
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HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
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HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
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writel(val, ®s->tx_instuffing);
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writel(0x0, ®s->tx_gydata0);
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writel(0x0, ®s->tx_gydata1);
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writel(0x0, ®s->tx_rcrdata0);
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writel(0x0, ®s->tx_rcrdata1);
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writel(0x0, ®s->tx_bcbdata0);
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writel(0x0, ®s->tx_bcbdata1);
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}
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static void hdmi_video_packetize(struct rk3288_hdmi *regs)
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{
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u32 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
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u32 remap_size = HDMI_VP_REMAP_YCC422_16BIT;
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u32 color_depth = 0;
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uint val, vp_conf;
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/* set the packetizer registers */
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val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
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HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
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((0 << HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
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HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
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writel(val, ®s->vp_pr_cd);
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clrsetbits_le32(®s->vp_stuff, HDMI_VP_STUFF_PR_STUFFING_MASK,
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HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE);
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/* data from pixel repeater block */
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vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
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HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
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clrsetbits_le32(®s->vp_conf, HDMI_VP_CONF_PR_EN_MASK |
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HDMI_VP_CONF_BYPASS_SELECT_MASK, vp_conf);
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clrsetbits_le32(®s->vp_stuff, HDMI_VP_STUFF_IDEFAULT_PHASE_MASK,
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1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET);
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writel(remap_size, ®s->vp_remap);
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vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
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HDMI_VP_CONF_PP_EN_DISABLE |
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HDMI_VP_CONF_YCC422_EN_DISABLE;
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clrsetbits_le32(®s->vp_conf, HDMI_VP_CONF_BYPASS_EN_MASK |
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HDMI_VP_CONF_PP_EN_ENMASK | HDMI_VP_CONF_YCC422_EN_MASK,
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vp_conf);
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clrsetbits_le32(®s->vp_stuff, HDMI_VP_STUFF_PP_STUFFING_MASK |
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HDMI_VP_STUFF_YCC422_STUFFING_MASK,
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HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
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HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE);
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clrsetbits_le32(®s->vp_conf, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
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output_select);
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}
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static inline void hdmi_phy_test_clear(struct rk3288_hdmi *regs, uint bit)
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{
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clrsetbits_le32(®s->phy_tst0, HDMI_PHY_TST0_TSTCLR_MASK,
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bit << HDMI_PHY_TST0_TSTCLR_OFFSET);
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}
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static int hdmi_phy_wait_i2c_done(struct rk3288_hdmi *regs, u32 msec)
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{
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ulong start;
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u32 val;
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start = get_timer(0);
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do {
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val = readl(®s->ih_i2cmphy_stat0);
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if (val & 0x3) {
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writel(val, ®s->ih_i2cmphy_stat0);
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return 0;
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}
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udelay(100);
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} while (get_timer(start) < msec);
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return 1;
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}
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static void hdmi_phy_i2c_write(struct rk3288_hdmi *regs, uint data, uint addr)
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{
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writel(0xff, ®s->ih_i2cmphy_stat0);
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writel(addr, ®s->phy_i2cm_address_addr);
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writel((u8)(data >> 8), ®s->phy_i2cm_datao_1_addr);
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writel((u8)(data >> 0), ®s->phy_i2cm_datao_0_addr);
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writel(HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
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®s->phy_i2cm_operation_addr);
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hdmi_phy_wait_i2c_done(regs, 1000);
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}
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static void hdmi_phy_enable_power(struct rk3288_hdmi *regs, uint enable)
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{
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clrsetbits_le32(®s->phy_conf0, HDMI_PHY_CONF0_PDZ_MASK,
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enable << HDMI_PHY_CONF0_PDZ_OFFSET);
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}
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static void hdmi_phy_enable_tmds(struct rk3288_hdmi *regs, uint enable)
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{
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clrsetbits_le32(®s->phy_conf0, HDMI_PHY_CONF0_ENTMDS_MASK,
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enable << HDMI_PHY_CONF0_ENTMDS_OFFSET);
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}
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static void hdmi_phy_enable_spare(struct rk3288_hdmi *regs, uint enable)
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{
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clrsetbits_le32(®s->phy_conf0, HDMI_PHY_CONF0_SPARECTRL_MASK,
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enable << HDMI_PHY_CONF0_SPARECTRL_OFFSET);
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}
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static void hdmi_phy_gen2_pddq(struct rk3288_hdmi *regs, uint enable)
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{
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clrsetbits_le32(®s->phy_conf0, HDMI_PHY_CONF0_GEN2_PDDQ_MASK,
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enable << HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET);
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}
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static void hdmi_phy_gen2_txpwron(struct rk3288_hdmi *regs, uint enable)
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{
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clrsetbits_le32(®s->phy_conf0,
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HDMI_PHY_CONF0_GEN2_TXPWRON_MASK,
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enable << HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET);
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}
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static void hdmi_phy_sel_data_en_pol(struct rk3288_hdmi *regs, uint enable)
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{
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clrsetbits_le32(®s->phy_conf0,
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HDMI_PHY_CONF0_SELDATAENPOL_MASK,
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enable << HDMI_PHY_CONF0_SELDATAENPOL_OFFSET);
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}
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static void hdmi_phy_sel_interface_control(struct rk3288_hdmi *regs,
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uint enable)
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{
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clrsetbits_le32(®s->phy_conf0, HDMI_PHY_CONF0_SELDIPIF_MASK,
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enable << HDMI_PHY_CONF0_SELDIPIF_OFFSET);
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}
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static int hdmi_phy_configure(struct rk3288_hdmi *regs, u32 mpixelclock)
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{
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ulong start;
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uint i, val;
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writel(HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS,
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®s->mc_flowctrl);
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/* gen2 tx power off */
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hdmi_phy_gen2_txpwron(regs, 0);
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/* gen2 pddq */
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hdmi_phy_gen2_pddq(regs, 1);
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/* phy reset */
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writel(HDMI_MC_PHYRSTZ_DEASSERT, ®s->mc_phyrstz);
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writel(HDMI_MC_PHYRSTZ_ASSERT, ®s->mc_phyrstz);
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writel(HDMI_MC_HEACPHY_RST_ASSERT, ®s->mc_heacphy_rst);
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hdmi_phy_test_clear(regs, 1);
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writel(HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2, ®s->phy_i2cm_slave_addr);
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hdmi_phy_test_clear(regs, 0);
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/* pll/mpll cfg - always match on final entry */
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for (i = 0; rockchip_mpll_cfg[i].mpixelclock != (~0ul); i++)
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if (mpixelclock <= rockchip_mpll_cfg[i].mpixelclock)
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break;
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hdmi_phy_i2c_write(regs, rockchip_mpll_cfg[i].cpce, PHY_OPMODE_PLLCFG);
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hdmi_phy_i2c_write(regs, rockchip_mpll_cfg[i].gmp, PHY_PLLGMPCTRL);
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hdmi_phy_i2c_write(regs, rockchip_mpll_cfg[i].curr, PHY_PLLCURRCTRL);
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hdmi_phy_i2c_write(regs, 0x0000, PHY_PLLPHBYCTRL);
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hdmi_phy_i2c_write(regs, 0x0006, PHY_PLLCLKBISTPHASE);
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for (i = 0; rockchip_phy_config[i].mpixelclock != (~0ul); i++)
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if (mpixelclock <= rockchip_phy_config[i].mpixelclock)
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break;
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/*
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* resistance term 133ohm cfg
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* preemp cgf 0.00
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* tx/ck lvl 10
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*/
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hdmi_phy_i2c_write(regs, rockchip_phy_config[i].term, PHY_TXTERM);
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hdmi_phy_i2c_write(regs, rockchip_phy_config[i].sym_ctr,
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PHY_CKSYMTXCTRL);
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hdmi_phy_i2c_write(regs, rockchip_phy_config[i].vlev_ctr, PHY_VLEVCTRL);
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/* remove clk term */
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hdmi_phy_i2c_write(regs, 0x8000, PHY_CKCALCTRL);
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hdmi_phy_enable_power(regs, 1);
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/* toggle tmds enable */
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hdmi_phy_enable_tmds(regs, 0);
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hdmi_phy_enable_tmds(regs, 1);
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/* gen2 tx power on */
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hdmi_phy_gen2_txpwron(regs, 1);
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hdmi_phy_gen2_pddq(regs, 0);
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hdmi_phy_enable_spare(regs, 1);
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/* wait for phy pll lock */
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start = get_timer(0);
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do {
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val = readl(®s->phy_stat0);
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if (!(val & HDMI_PHY_TX_PHY_LOCK))
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return 0;
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udelay(100);
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} while (get_timer(start) < 5);
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return -1;
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}
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static int hdmi_phy_init(struct rk3288_hdmi *regs, uint mpixelclock)
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{
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int i, ret;
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/* hdmi phy spec says to do the phy initialization sequence twice */
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for (i = 0; i < 2; i++) {
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hdmi_phy_sel_data_en_pol(regs, 1);
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hdmi_phy_sel_interface_control(regs, 0);
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hdmi_phy_enable_tmds(regs, 0);
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hdmi_phy_enable_power(regs, 0);
|
|
|
|
ret = hdmi_phy_configure(regs, mpixelclock);
|
|
if (ret) {
|
|
debug("hdmi phy config failure %d\n", ret);
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void hdmi_av_composer(struct rk3288_hdmi *regs,
|
|
const struct display_timing *edid)
|
|
{
|
|
bool mdataenablepolarity = true;
|
|
uint inv_val;
|
|
uint hbl;
|
|
uint vbl;
|
|
|
|
hbl = edid->hback_porch.typ + edid->hfront_porch.typ +
|
|
edid->hsync_len.typ;
|
|
vbl = edid->vback_porch.typ + edid->vfront_porch.typ +
|
|
edid->vsync_len.typ;
|
|
|
|
/* set up hdmi_fc_invidconf */
|
|
inv_val = HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE;
|
|
|
|
inv_val |= (edid->flags & DISPLAY_FLAGS_HSYNC_HIGH ?
|
|
HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
|
|
HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW);
|
|
|
|
inv_val |= (edid->flags & DISPLAY_FLAGS_VSYNC_HIGH ?
|
|
HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
|
|
HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW);
|
|
|
|
inv_val |= (mdataenablepolarity ?
|
|
HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
|
|
HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
|
|
|
|
/*
|
|
* TODO(sjg@chromium.org>: Need to check for HDMI / DVI
|
|
* inv_val |= (edid->hdmi_monitor_detected ?
|
|
* HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE :
|
|
* HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE);
|
|
*/
|
|
inv_val |= HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE;
|
|
|
|
inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW;
|
|
|
|
inv_val |= HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE;
|
|
|
|
writel(inv_val, ®s->fc_invidconf);
|
|
|
|
/* set up horizontal active pixel width */
|
|
writel(edid->hactive.typ >> 8, ®s->fc_inhactv1);
|
|
writel(edid->hactive.typ, ®s->fc_inhactv0);
|
|
|
|
/* set up vertical active lines */
|
|
writel(edid->vactive.typ >> 8, ®s->fc_invactv1);
|
|
writel(edid->vactive.typ, ®s->fc_invactv0);
|
|
|
|
/* set up horizontal blanking pixel region width */
|
|
writel(hbl >> 8, ®s->fc_inhblank1);
|
|
writel(hbl, ®s->fc_inhblank0);
|
|
|
|
/* set up vertical blanking pixel region width */
|
|
writel(vbl, ®s->fc_invblank);
|
|
|
|
/* set up hsync active edge delay width (in pixel clks) */
|
|
writel(edid->hfront_porch.typ >> 8, ®s->fc_hsyncindelay1);
|
|
writel(edid->hfront_porch.typ, ®s->fc_hsyncindelay0);
|
|
|
|
/* set up vsync active edge delay (in lines) */
|
|
writel(edid->vfront_porch.typ, ®s->fc_vsyncindelay);
|
|
|
|
/* set up hsync active pulse width (in pixel clks) */
|
|
writel(edid->hsync_len.typ >> 8, ®s->fc_hsyncinwidth1);
|
|
writel(edid->hsync_len.typ, ®s->fc_hsyncinwidth0);
|
|
|
|
/* set up vsync active edge delay (in lines) */
|
|
writel(edid->vsync_len.typ, ®s->fc_vsyncinwidth);
|
|
}
|
|
|
|
/* hdmi initialization step b.4 */
|
|
static void hdmi_enable_video_path(struct rk3288_hdmi *regs)
|
|
{
|
|
uint clkdis;
|
|
|
|
/* control period minimum duration */
|
|
writel(12, ®s->fc_ctrldur);
|
|
writel(32, ®s->fc_exctrldur);
|
|
writel(1, ®s->fc_exctrlspac);
|
|
|
|
/* set to fill tmds data channels */
|
|
writel(0x0b, ®s->fc_ch0pream);
|
|
writel(0x16, ®s->fc_ch1pream);
|
|
writel(0x21, ®s->fc_ch2pream);
|
|
|
|
/* enable pixel clock and tmds data path */
|
|
clkdis = 0x7f;
|
|
clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
|
|
writel(clkdis, ®s->mc_clkdis);
|
|
|
|
clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
|
|
writel(clkdis, ®s->mc_clkdis);
|
|
|
|
clkdis &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE;
|
|
writel(clkdis, ®s->mc_clkdis);
|
|
}
|
|
|
|
/* workaround to clear the overflow condition */
|
|
static void hdmi_clear_overflow(struct rk3288_hdmi *regs)
|
|
{
|
|
uint val, count;
|
|
|
|
/* tmds software reset */
|
|
writel((u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, ®s->mc_swrstz);
|
|
|
|
val = readl(®s->fc_invidconf);
|
|
|
|
for (count = 0; count < 4; count++)
|
|
writel(val, ®s->fc_invidconf);
|
|
}
|
|
|
|
static void hdmi_audio_set_format(struct rk3288_hdmi *regs)
|
|
{
|
|
writel(HDMI_AUD_CONF0_I2S_SELECT | HDMI_AUD_CONF0_I2S_IN_EN_0,
|
|
®s->aud_conf0);
|
|
|
|
|
|
writel(HDMI_AUD_CONF1_I2S_MODE_STANDARD_MODE |
|
|
HDMI_AUD_CONF1_I2S_WIDTH_16BIT, ®s->aud_conf1);
|
|
|
|
writel(0x00, ®s->aud_conf2);
|
|
}
|
|
|
|
static void hdmi_audio_fifo_reset(struct rk3288_hdmi *regs)
|
|
{
|
|
writel((u8)~HDMI_MC_SWRSTZ_II2SSWRST_REQ, ®s->mc_swrstz);
|
|
writel(HDMI_AUD_CONF0_SW_AUDIO_FIFO_RST, ®s->aud_conf0);
|
|
|
|
writel(0x00, ®s->aud_int);
|
|
writel(0x00, ®s->aud_int1);
|
|
}
|
|
|
|
static void hdmi_init_interrupt(struct rk3288_hdmi *regs)
|
|
{
|
|
uint ih_mute;
|
|
|
|
/*
|
|
* boot up defaults are:
|
|
* hdmi_ih_mute = 0x03 (disabled)
|
|
* hdmi_ih_mute_* = 0x00 (enabled)
|
|
*
|
|
* disable top level interrupt bits in hdmi block
|
|
*/
|
|
ih_mute = readl(®s->ih_mute) |
|
|
HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
|
|
HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
|
|
|
|
writel(ih_mute, ®s->ih_mute);
|
|
|
|
/* enable i2c master done irq */
|
|
writel(~0x04, ®s->i2cm_int);
|
|
|
|
/* enable i2c client nack % arbitration error irq */
|
|
writel(~0x44, ®s->i2cm_ctlint);
|
|
|
|
/* enable phy i2cm done irq */
|
|
writel(HDMI_PHY_I2CM_INT_ADDR_DONE_POL, ®s->phy_i2cm_int_addr);
|
|
|
|
/* enable phy i2cm nack & arbitration error irq */
|
|
writel(HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
|
|
HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
|
|
®s->phy_i2cm_ctlint_addr);
|
|
|
|
/* enable cable hot plug irq */
|
|
writel((u8)~HDMI_PHY_HPD, ®s->phy_mask0);
|
|
|
|
/* clear hotplug interrupts */
|
|
writel(HDMI_IH_PHY_STAT0_HPD, ®s->ih_phy_stat0);
|
|
}
|
|
|
|
static int hdmi_get_plug_in_status(struct rk3288_hdmi *regs)
|
|
{
|
|
uint val = readl(®s->phy_stat0) & HDMI_PHY_HPD;
|
|
|
|
return !!val;
|
|
}
|
|
|
|
static int hdmi_wait_for_hpd(struct rk3288_hdmi *regs)
|
|
{
|
|
ulong start;
|
|
|
|
start = get_timer(0);
|
|
do {
|
|
if (hdmi_get_plug_in_status(regs))
|
|
return 0;
|
|
udelay(100);
|
|
} while (get_timer(start) < 300);
|
|
|
|
return -1;
|
|
}
|
|
|
|
static int hdmi_ddc_wait_i2c_done(struct rk3288_hdmi *regs, int msec)
|
|
{
|
|
u32 val;
|
|
ulong start;
|
|
|
|
start = get_timer(0);
|
|
do {
|
|
val = readl(®s->ih_i2cm_stat0);
|
|
if (val & 0x2) {
|
|
writel(val, ®s->ih_i2cm_stat0);
|
|
return 0;
|
|
}
|
|
|
|
udelay(100);
|
|
} while (get_timer(start) < msec);
|
|
|
|
return 1;
|
|
}
|
|
|
|
static void hdmi_ddc_reset(struct rk3288_hdmi *regs)
|
|
{
|
|
clrbits_le32(®s->i2cm_softrstz, HDMI_I2CM_SOFTRSTZ);
|
|
}
|
|
|
|
static int hdmi_read_edid(struct rk3288_hdmi *regs, int block, u8 *buff)
|
|
{
|
|
int shift = (block % 2) * 0x80;
|
|
int edid_read_err = 0;
|
|
u32 trytime = 5;
|
|
u32 n, j, val;
|
|
|
|
/* set ddc i2c clk which devided from ddc_clk to 100khz */
|
|
writel(0x7a, ®s->i2cm_ss_scl_hcnt_0_addr);
|
|
writel(0x8d, ®s->i2cm_ss_scl_lcnt_0_addr);
|
|
|
|
/*
|
|
* TODO(sjg@chromium.org): The above values don't work - these ones
|
|
* work better, but generate lots of errors in the data.
|
|
*/
|
|
writel(0x0d, ®s->i2cm_ss_scl_hcnt_0_addr);
|
|
writel(0x0d, ®s->i2cm_ss_scl_lcnt_0_addr);
|
|
clrsetbits_le32(®s->i2cm_div, HDMI_I2CM_DIV_FAST_STD_MODE,
|
|
HDMI_I2CM_DIV_STD_MODE);
|
|
|
|
writel(HDMI_I2CM_SLAVE_DDC_ADDR, ®s->i2cm_slave);
|
|
writel(HDMI_I2CM_SEGADDR_DDC, ®s->i2cm_segaddr);
|
|
writel(block >> 1, ®s->i2cm_segptr);
|
|
|
|
while (trytime--) {
|
|
edid_read_err = 0;
|
|
|
|
for (n = 0; n < HDMI_EDID_BLOCK_SIZE / 8; n++) {
|
|
writel(shift + 8 * n, ®s->i2c_address);
|
|
|
|
if (block == 0)
|
|
clrsetbits_le32(®s->i2cm_operation,
|
|
HDMI_I2CM_OPT_RD8,
|
|
HDMI_I2CM_OPT_RD8);
|
|
else
|
|
clrsetbits_le32(®s->i2cm_operation,
|
|
HDMI_I2CM_OPT_RD8_EXT,
|
|
HDMI_I2CM_OPT_RD8_EXT);
|
|
|
|
if (hdmi_ddc_wait_i2c_done(regs, 10)) {
|
|
hdmi_ddc_reset(regs);
|
|
edid_read_err = 1;
|
|
break;
|
|
}
|
|
|
|
for (j = 0; j < 8; j++) {
|
|
val = readl(®s->i2cm_buf0 + j);
|
|
buff[8 * n + j] = val;
|
|
}
|
|
}
|
|
|
|
if (!edid_read_err)
|
|
break;
|
|
}
|
|
|
|
return edid_read_err;
|
|
}
|
|
|
|
static const u8 pre_buf[] = {
|
|
0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
|
|
0x04, 0x69, 0xfa, 0x23, 0xc8, 0x28, 0x01, 0x00,
|
|
0x10, 0x17, 0x01, 0x03, 0x80, 0x33, 0x1d, 0x78,
|
|
0x2a, 0xd9, 0x45, 0xa2, 0x55, 0x4d, 0xa0, 0x27,
|
|
0x12, 0x50, 0x54, 0xb7, 0xef, 0x00, 0x71, 0x4f,
|
|
0x81, 0x40, 0x81, 0x80, 0x95, 0x00, 0xb3, 0x00,
|
|
0xd1, 0xc0, 0x81, 0xc0, 0x81, 0x00, 0x02, 0x3a,
|
|
0x80, 0x18, 0x71, 0x38, 0x2d, 0x40, 0x58, 0x2c,
|
|
0x45, 0x00, 0xfd, 0x1e, 0x11, 0x00, 0x00, 0x1e,
|
|
0x00, 0x00, 0x00, 0xff, 0x00, 0x44, 0x34, 0x4c,
|
|
0x4d, 0x54, 0x46, 0x30, 0x37, 0x35, 0x39, 0x37,
|
|
0x36, 0x0a, 0x00, 0x00, 0x00, 0xfd, 0x00, 0x32,
|
|
0x4b, 0x18, 0x53, 0x11, 0x00, 0x0a, 0x20, 0x20,
|
|
0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0xfc,
|
|
0x00, 0x41, 0x53, 0x55, 0x53, 0x20, 0x56, 0x53,
|
|
0x32, 0x33, 0x38, 0x0a, 0x20, 0x20, 0x01, 0xb0,
|
|
0x02, 0x03, 0x22, 0x71, 0x4f, 0x01, 0x02, 0x03,
|
|
0x11, 0x12, 0x13, 0x04, 0x14, 0x05, 0x0e, 0x0f,
|
|
0x1d, 0x1e, 0x1f, 0x10, 0x23, 0x09, 0x17, 0x07,
|
|
0x83, 0x01, 0x00, 0x00, 0x65, 0x03, 0x0c, 0x00,
|
|
0x10, 0x00, 0x8c, 0x0a, 0xd0, 0x8a, 0x20, 0xe0,
|
|
0x2d, 0x10, 0x10, 0x3e, 0x96, 0x00, 0xfd, 0x1e,
|
|
0x11, 0x00, 0x00, 0x18, 0x01, 0x1d, 0x00, 0x72,
|
|
0x51, 0xd0, 0x1e, 0x20, 0x6e, 0x28, 0x55, 0x00,
|
|
0xfd, 0x1e, 0x11, 0x00, 0x00, 0x1e, 0x01, 0x1d,
|
|
0x00, 0xbc, 0x52, 0xd0, 0x1e, 0x20, 0xb8, 0x28,
|
|
0x55, 0x40, 0xfd, 0x1e, 0x11, 0x00, 0x00, 0x1e,
|
|
0x8c, 0x0a, 0xd0, 0x90, 0x20, 0x40, 0x31, 0x20,
|
|
0x0c, 0x40, 0x55, 0x00, 0xfd, 0x1e, 0x11, 0x00,
|
|
0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe9,
|
|
};
|
|
|
|
static int rk_hdmi_read_edid(struct udevice *dev, u8 *buf, int buf_size)
|
|
{
|
|
struct rk_hdmi_priv *priv = dev_get_priv(dev);
|
|
u32 edid_size = HDMI_EDID_BLOCK_SIZE;
|
|
int ret;
|
|
|
|
if (0) {
|
|
edid_size = sizeof(pre_buf);
|
|
memcpy(buf, pre_buf, edid_size);
|
|
} else {
|
|
ret = hdmi_read_edid(priv->regs, 0, buf);
|
|
if (ret) {
|
|
debug("failed to read edid.\n");
|
|
return -1;
|
|
}
|
|
|
|
if (buf[0x7e] != 0) {
|
|
hdmi_read_edid(priv->regs, 1,
|
|
buf + HDMI_EDID_BLOCK_SIZE);
|
|
edid_size += HDMI_EDID_BLOCK_SIZE;
|
|
}
|
|
}
|
|
|
|
return edid_size;
|
|
}
|
|
|
|
static int rk_hdmi_enable(struct udevice *dev, int panel_bpp,
|
|
const struct display_timing *edid)
|
|
{
|
|
struct rk_hdmi_priv *priv = dev_get_priv(dev);
|
|
struct rk3288_hdmi *regs = priv->regs;
|
|
int ret;
|
|
|
|
debug("hdmi, mode info : clock %d hdis %d vdis %d\n",
|
|
edid->pixelclock.typ, edid->hactive.typ, edid->vactive.typ);
|
|
|
|
hdmi_av_composer(regs, edid);
|
|
|
|
ret = hdmi_phy_init(regs, edid->pixelclock.typ);
|
|
if (ret)
|
|
return ret;
|
|
|
|
hdmi_enable_video_path(regs);
|
|
|
|
hdmi_audio_fifo_reset(regs);
|
|
hdmi_audio_set_format(regs);
|
|
hdmi_audio_set_samplerate(regs, edid->pixelclock.typ);
|
|
|
|
hdmi_video_packetize(regs);
|
|
hdmi_video_sample(regs);
|
|
|
|
hdmi_clear_overflow(regs);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int rk_hdmi_ofdata_to_platdata(struct udevice *dev)
|
|
{
|
|
struct rk_hdmi_priv *priv = dev_get_priv(dev);
|
|
|
|
priv->regs = (struct rk3288_hdmi *)dev_get_addr(dev);
|
|
priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int rk_hdmi_probe(struct udevice *dev)
|
|
{
|
|
struct display_plat *uc_plat = dev_get_uclass_platdata(dev);
|
|
struct rk_hdmi_priv *priv = dev_get_priv(dev);
|
|
struct udevice *reg;
|
|
struct clk clk;
|
|
int ret;
|
|
int vop_id = uc_plat->source_id;
|
|
|
|
ret = clk_get_by_index(dev, 0, &clk);
|
|
if (ret >= 0) {
|
|
ret = clk_set_rate(&clk, 0);
|
|
clk_free(&clk);
|
|
}
|
|
if (ret) {
|
|
debug("%s: Failed to set hdmi clock: ret=%d\n", __func__, ret);
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* Configure the maximum clock to permit whatever resolution the
|
|
* monitor wants
|
|
*/
|
|
ret = clk_get_by_index(uc_plat->src_dev, 0, &clk);
|
|
if (ret >= 0) {
|
|
ret = clk_set_rate(&clk, 384000000);
|
|
clk_free(&clk);
|
|
}
|
|
if (ret < 0) {
|
|
debug("%s: Failed to set clock in source device '%s': ret=%d\n",
|
|
__func__, uc_plat->src_dev->name, ret);
|
|
return ret;
|
|
}
|
|
|
|
ret = regulator_get_by_platname("vcc50_hdmi", ®);
|
|
if (!ret)
|
|
ret = regulator_set_enable(reg, true);
|
|
if (ret)
|
|
debug("%s: Cannot set regulator vcc50_hdmi\n", __func__);
|
|
|
|
/* hdmi source select hdmi controller */
|
|
rk_setreg(&priv->grf->soc_con6, 1 << 15);
|
|
|
|
/* hdmi data from vop id */
|
|
rk_clrsetreg(&priv->grf->soc_con6, 1 << 4,
|
|
(vop_id == 1) ? (1 << 4) : 0);
|
|
|
|
ret = hdmi_wait_for_hpd(priv->regs);
|
|
if (ret < 0) {
|
|
debug("hdmi can not get hpd signal\n");
|
|
return -1;
|
|
}
|
|
|
|
hdmi_init_interrupt(priv->regs);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct dm_display_ops rk_hdmi_ops = {
|
|
.read_edid = rk_hdmi_read_edid,
|
|
.enable = rk_hdmi_enable,
|
|
};
|
|
|
|
static const struct udevice_id rk_hdmi_ids[] = {
|
|
{ .compatible = "rockchip,rk3288-dw-hdmi" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(hdmi_rockchip) = {
|
|
.name = "hdmi_rockchip",
|
|
.id = UCLASS_DISPLAY,
|
|
.of_match = rk_hdmi_ids,
|
|
.ops = &rk_hdmi_ops,
|
|
.ofdata_to_platdata = rk_hdmi_ofdata_to_platdata,
|
|
.probe = rk_hdmi_probe,
|
|
.priv_auto_alloc_size = sizeof(struct rk_hdmi_priv),
|
|
};
|