mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-06 19:26:16 +09:00
30677deefd
Environment variable mcinitcmd is defined to initiate MC and DPL deployment from the location where it is stored (NOR, NAND, SD, SATA, USB) during booting. If this variable is not defined then macro MC_BOOT_ENV_VAR will be null and MC will not be booted and DPL will not be applied during U-boot booting. Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
114 lines
2.9 KiB
C
114 lines
2.9 KiB
C
/*
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* Copyright 2015 Freescale Semiconductor, Inc.
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*
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <command.h>
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#include <netdev.h>
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#include <malloc.h>
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#include <fsl_mdio.h>
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#include <miiphy.h>
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#include <phy.h>
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#include <fm_eth.h>
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#include <asm/io.h>
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#include <exports.h>
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#include <asm/arch/fsl_serdes.h>
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#include <fsl-mc/ldpaa_wriop.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define MC_BOOT_ENV_VAR "mcinitcmd"
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int board_eth_init(bd_t *bis)
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{
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#if defined(CONFIG_FSL_MC_ENET)
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char *mc_boot_env_var;
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int i, interface;
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struct memac_mdio_info mdio_info;
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struct mii_dev *dev;
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struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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u32 srds_s1;
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struct memac_mdio_controller *reg;
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srds_s1 = in_le32(&gur->rcwsr[28]) &
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FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
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srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
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reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
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mdio_info.regs = reg;
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mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
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/* Register the EMI 1 */
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fm_memac_mdio_init(bis, &mdio_info);
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reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
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mdio_info.regs = reg;
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mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
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/* Register the EMI 2 */
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fm_memac_mdio_init(bis, &mdio_info);
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switch (srds_s1) {
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case 0x2A:
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wriop_set_phy_address(WRIOP1_DPMAC1, CORTINA_PHY_ADDR1);
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wriop_set_phy_address(WRIOP1_DPMAC2, CORTINA_PHY_ADDR2);
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wriop_set_phy_address(WRIOP1_DPMAC3, CORTINA_PHY_ADDR3);
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wriop_set_phy_address(WRIOP1_DPMAC4, CORTINA_PHY_ADDR4);
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wriop_set_phy_address(WRIOP1_DPMAC5, AQ_PHY_ADDR1);
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wriop_set_phy_address(WRIOP1_DPMAC6, AQ_PHY_ADDR2);
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wriop_set_phy_address(WRIOP1_DPMAC7, AQ_PHY_ADDR3);
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wriop_set_phy_address(WRIOP1_DPMAC8, AQ_PHY_ADDR4);
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break;
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default:
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printf("SerDes1 protocol 0x%x is not supported on LS2080aRDB\n",
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srds_s1);
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break;
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}
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for (i = WRIOP1_DPMAC1; i <= WRIOP1_DPMAC4; i++) {
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interface = wriop_get_enet_if(i);
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switch (interface) {
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case PHY_INTERFACE_MODE_XGMII:
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dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
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wriop_set_mdio(i, dev);
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break;
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default:
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break;
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}
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}
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for (i = WRIOP1_DPMAC5; i <= WRIOP1_DPMAC8; i++) {
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switch (wriop_get_enet_if(i)) {
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case PHY_INTERFACE_MODE_XGMII:
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dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
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wriop_set_mdio(i, dev);
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break;
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default:
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break;
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}
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}
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mc_boot_env_var = getenv(MC_BOOT_ENV_VAR);
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if (mc_boot_env_var)
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run_command_list(mc_boot_env_var, -1, 0);
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cpu_eth_init(bis);
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#endif /* CONFIG_FMAN_ENET */
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#ifdef CONFIG_PHY_AQUANTIA
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/*
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* Export functions to be used by AQ firmware
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* upload application
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*/
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gd->jt->strcpy = strcpy;
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gd->jt->mdelay = mdelay;
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gd->jt->mdio_get_current_dev = mdio_get_current_dev;
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gd->jt->phy_find_by_mask = phy_find_by_mask;
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gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
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gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
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#endif
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return pci_eth_init(bis);
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}
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