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The QorIQ LS2088A SoC is built on layerscape architecture. It is similar to LS2080A SoC with some differences like 1)Timer controller offset is different 2)It has A72 cores 3)It supports TZASC module Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
82 lines
2.8 KiB
Plaintext
82 lines
2.8 KiB
Plaintext
Overview
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--------
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The LS2080A Reference Design (RDB) is a high-performance computing,
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evaluation, and development platform that supports the QorIQ LS2080A, LS2088A
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Layerscape Architecture processor.
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LS2080A, LS2088A SoC Overview
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--------------------
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Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A,
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LS2088A SoC overview.
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LS2080ARDB board Overview
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-----------------------
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- SERDES Connections, 16 lanes supporting:
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- PCI Express - 3.0
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- SATA 3.0
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- XFI
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- DDR Controller
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- Two ports of 72-bits (8-bits ECC) DDR4. Each port supports four
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chip-selects and two DIMM connectors. Support is up to 2133MT/s.
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- One port of 40-bits (8-bits ECC) DDR4 which supports four chip-selects
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and two DIMM connectors. Support is up to 1600MT/s.
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-IFC/Local Bus
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- IFC rev. 2.0 implementation supporting Little Endian connection scheme.
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- 128 MB NOR flash 16-bit data bus
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- One 2 GB NAND flash with ECC support
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- CPLD connection
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- USB 3.0
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- Two high speed USB 3.0 ports
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- First USB 3.0 port configured as Host with Type-A connector
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- Second USB 3.0 port configured as OTG with micro-AB connector
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- SDHC adapter
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- SD Card Rev 2.0 and Rev 3.0
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- DSPI
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- 128 MB high-speed flash Memory for boot code and storage (up to 108MHz)
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- 4 I2C controllers
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- Two SATA onboard connectors
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- UART
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- ARM JTAG support
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Memory map from core's view
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----------------------------
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0x00_0000_0000 .. 0x00_000F_FFFF Boot Rom
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0x00_0100_0000 .. 0x00_0FFF_FFFF CCSR
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0x00_1800_0000 .. 0x00_181F_FFFF OCRAM
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0x00_3000_0000 .. 0x00_3FFF_FFFF IFC region #1
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0x00_8000_0000 .. 0x00_FFFF_FFFF DDR region #1
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0x05_1000_0000 .. 0x05_FFFF_FFFF IFC region #2
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0x80_8000_0000 .. 0xFF_FFFF_FFFF DDR region #2
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Other addresses are either reserved, or not used directly by U-Boot.
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This list should be updated when more addresses are used.
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IFC region map from core's view
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-------------------------------
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During boot i.e. IFC Region #1:-
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0x30000000 - 0x37ffffff : 128MB : NOR flash
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0x3C000000 - 0x40000000 : 64MB : CPLD
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After relocate to DDR i.e. IFC Region #2:-
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0x5_1000_0000..0x5_1fff_ffff Memory Hole
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0x5_2000_0000..0x5_3fff_ffff IFC CSx (CPLD, NAND and others 512MB)
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0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB
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0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
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0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
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Booting Options
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---------------
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a) NOR boot
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b) NAND boot
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Booting Linux flavors which do not support 48-bit VA (< Linux 3.18)
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-------------------------------------------------------------------
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One needs to use appropriate bootargs to boot Linux flavors which do
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not support 48-bit VA (for e.g. < Linux 3.18) by appending mem=2048M, as shown
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below:
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=> setenv bootargs 'console=ttyS1,115200 root=/dev/ram
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earlycon=uart8250,mmio,0x21c0600,115200 default_hugepagesz=2m hugepagesz=2m
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hugepages=16 mem=2048M'
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