mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
da34aae5fb
The gpio spec for bf54x and bf60x differ a lot from the old gpio driver for bf5xx. A lot of machine macros are used to accomodate both code in one gpio driver. This patch split the old gpio driver and move new gpio2 support to the generic gpio driver folder. - To enable gpio2 driver, macro CONFIG_ADI_GPIO2 should be defined in the board's config header file. - The gpio2 driver supports bf54x, bf60x and future ADI processors, while the older gpio driver supports bf50x, bf51x, bf52x, bf53x and bf561. - All blackfin specific gpio function names are replaced by the generic gpio APIs. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
213 lines
5.0 KiB
C
213 lines
5.0 KiB
C
/*
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* U-boot - Configuration file for BF548 STAMP board
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*/
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#ifndef __CONFIG_BF548_EZKIT_H__
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#define __CONFIG_BF548_EZKIT_H__
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#include <asm/config-pre.h>
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/*
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* Processor Settings
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*/
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#define CONFIG_BFIN_CPU bf548-0.0
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#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
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/*
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* Clock Settings
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* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
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* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
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*/
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/* CONFIG_CLKIN_HZ is any value in Hz */
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#define CONFIG_CLKIN_HZ 25000000
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/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
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/* 1 = CLKIN / 2 */
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#define CONFIG_CLKIN_HALF 0
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/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
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/* 1 = bypass PLL */
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#define CONFIG_PLL_BYPASS 0
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/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
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/* Values can range from 0-63 (where 0 means 64) */
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#define CONFIG_VCO_MULT 21
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/* CCLK_DIV controls the core clock divider */
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/* Values can be 1, 2, 4, or 8 ONLY */
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#define CONFIG_CCLK_DIV 1
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/* SCLK_DIV controls the system clock divider */
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/* Values can range from 1-15 */
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#define CONFIG_SCLK_DIV 4
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/*
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* Memory Settings
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*/
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#define CONFIG_MEM_ADD_WDTH 10
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#define CONFIG_MEM_SIZE 64
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#define CONFIG_EBIU_DDRCTL0_VAL 0x218A83FE
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#define CONFIG_EBIU_DDRCTL1_VAL 0x20022222
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#define CONFIG_EBIU_DDRCTL2_VAL 0x00000021
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/* Default EZ-Kit bank mapping:
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* Async Bank 0 - 32MB Burst Flash
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* Async Bank 1 - Ethernet
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* Async Bank 2 - Nothing
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* Async Bank 3 - Nothing
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*/
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#define CONFIG_EBIU_AMGCTL_VAL 0xFF
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#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
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#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
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#define CONFIG_EBIU_FCTL_VAL (BCLK_4)
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#define CONFIG_EBIU_MODE_VAL (B0MODE_FLASH)
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#define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
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#define CONFIG_SYS_MALLOC_LEN (768 * 1024)
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/*
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* Network Settings
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*/
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#define ADI_CMDS_NETWORK 1
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#define CONFIG_SMC911X 1
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#define CONFIG_SMC911X_BASE 0x24000000
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#define CONFIG_SMC911X_16_BIT
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#define CONFIG_HOSTNAME bf548-ezkit
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/* Uncomment next line to use fixed MAC address */
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/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
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/*
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* Flash Settings
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*/
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_BASE 0x20000000
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_SYS_FLASH_PROTECTION
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_SYS_MAX_FLASH_SECT 259
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/*
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* SPI Settings
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*/
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#define CONFIG_BFIN_SPI
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#define CONFIG_ENV_SPI_MAX_HZ 30000000
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#define CONFIG_SF_DEFAULT_SPEED 30000000
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#define CONFIG_SPI_FLASH
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#define CONFIG_SPI_FLASH_STMICRO
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/*
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* Env Storage Settings
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*/
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#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
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#define CONFIG_ENV_IS_IN_SPI_FLASH
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#define CONFIG_ENV_OFFSET 0x10000
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_ENV_SECT_SIZE 0x10000
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#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
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#elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
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#define CONFIG_ENV_IS_IN_NAND
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#define CONFIG_ENV_OFFSET 0x60000
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#define CONFIG_ENV_SIZE 0x20000
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#else
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/* The BF548-EZKIT uses a top boot flash */
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
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#define CONFIG_ENV_OFFSET (0x1000000 - CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
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#define CONFIG_ENV_SECT_SIZE 0x8000
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#endif
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/*
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* NAND Settings
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*/
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#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
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#define CONFIG_BFIN_NFC_CTL_VAL 0x0033
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#define CONFIG_BFIN_NFC_BOOTROM_ECC
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#define CONFIG_DRIVER_NAND_BFIN
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#define CONFIG_SYS_NAND_BASE 0 /* not actually used */
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#endif
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/*
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* I2C Settings
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*/
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#define CONFIG_BFIN_TWI_I2C 1
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#define CONFIG_HARD_I2C 1
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/*
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* SATA
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*/
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#if !defined(__ADSPBF544__)
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#define CONFIG_LIBATA
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#define CONFIG_SYS_SATA_MAX_DEVICE 1
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#define CONFIG_LBA48
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#define CONFIG_PATA_BFIN
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#define CONFIG_BFIN_ATAPI_BASE_ADDR 0xFFC03800
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#define CONFIG_BFIN_ATA_MODE XFER_PIO_4
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#endif
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/*
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* SDH Settings
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*/
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#if !defined(__ADSPBF544__)
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#define CONFIG_GENERIC_MMC
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#define CONFIG_MMC
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#define CONFIG_BFIN_SDH
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#endif
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/*
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* USB Settings
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*/
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#if !defined(__ADSPBF544__)
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#define CONFIG_USB
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#define CONFIG_MUSB_HCD
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#define CONFIG_USB_BLACKFIN
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#define CONFIG_USB_STORAGE
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#define CONFIG_MUSB_TIMEOUT 100000
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#endif
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/*
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* Misc Settings
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*/
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#define CONFIG_BOARD_EARLY_INIT_F
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#define CONFIG_BOARD_SIZE_LIMIT $$(( 512 * 1024 ))
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#define CONFIG_RTC_BFIN
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#define CONFIG_UART_CONSOLE 1
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#define CONFIG_BFIN_SPI_IMG_SIZE 0x50000
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#define CONFIG_ADI_GPIO2
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#undef CONFIG_VIDEO
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#ifdef CONFIG_VIDEO
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#define EASYLOGO_HEADER < asm/bfin_logo_230x230_gzip.h >
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#define CONFIG_DEB_DMA_URGENT
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#endif
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/* Define if want to do post memory test */
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#undef CONFIG_POST
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#ifdef CONFIG_POST
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#define CONFIG_POST_BSPEC1_GPIO_LEDS \
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GPIO_PG6, GPIO_PG7, GPIO_PG8, GPIO_PG9, GPIO_PG10, GPIO_PG11,
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#define CONFIG_POST_BSPEC2_GPIO_BUTTONS \
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GPIO_PB8, GPIO_PB9, GPIO_PB10, GPIO_PB11
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#define CONFIG_POST_BSPEC2_GPIO_NAMES \
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13, 12, 11, 10,
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#define CONFIG_SYS_POST_FLASH_START 10
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#define CONFIG_SYS_POST_FLASH_END 127
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#endif
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/*
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* Pull in common ADI header for remaining command/environment setup
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*/
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#include <configs/bfin_adi_common.h>
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#endif
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