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https://github.com/brain-hackers/u-boot-brain
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c93adc08f3
Add Reset Driver configuration to ast2500 SoC Device Tree and bindings for various reset signals Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
64 lines
1.1 KiB
Plaintext
64 lines
1.1 KiB
Plaintext
#include <dt-bindings/clock/ast2500-scu.h>
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#include <dt-bindings/reset/ast2500-reset.h>
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#include "ast2500.dtsi"
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/ {
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scu: clock-controller@1e6e2000 {
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compatible = "aspeed,ast2500-scu";
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reg = <0x1e6e2000 0x1000>;
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u-boot,dm-pre-reloc;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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rst: reset-controller {
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u-boot,dm-pre-reloc;
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compatible = "aspeed,ast2500-reset";
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aspeed,wdt = <&wdt1>;
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#reset-cells = <1>;
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};
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sdrammc: sdrammc@1e6e0000 {
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u-boot,dm-pre-reloc;
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compatible = "aspeed,ast2500-sdrammc";
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reg = <0x1e6e0000 0x174
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0x1e6e0200 0x1d4 >;
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#reset-cells = <1>;
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clocks = <&scu PLL_MPLL>;
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resets = <&rst AST_RESET_SDRAM>;
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};
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ahb {
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u-boot,dm-pre-reloc;
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apb {
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u-boot,dm-pre-reloc;
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timer: timer@1e782000 {
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u-boot,dm-pre-reloc;
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};
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uart1: serial@1e783000 {
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clocks = <&scu PCLK_UART1>;
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};
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uart2: serial@1e78d000 {
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clocks = <&scu PCLK_UART2>;
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};
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uart3: serial@1e78e000 {
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clocks = <&scu PCLK_UART3>;
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};
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uart4: serial@1e78f000 {
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clocks = <&scu PCLK_UART4>;
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};
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uart5: serial@1e784000 {
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clocks = <&scu PCLK_UART5>;
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};
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};
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};
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};
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