mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-09 12:46:17 +09:00
c93ad777b8
Some of these options are not used by the driver anymore and some of them are obsolete as the information is gathered from the dt. Also consolidating defines in common headers. Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
124 lines
3.4 KiB
C
124 lines
3.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2020 NXP
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* Copyright 2016 Freescale Semiconductor, Inc.
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*/
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#ifndef __LS1012ARDB_H__
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#define __LS1012ARDB_H__
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#include "ls1012a_common.h"
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/* DDR */
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#define CONFIG_DIMM_SLOTS_PER_CTLR 1
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#define CONFIG_CHIP_SELECTS_PER_CTRL 1
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#define CONFIG_SYS_SDRAM_SIZE 0x40000000
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#define CONFIG_CMD_MEMINFO
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/*
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* I2C IO expander
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*/
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#define I2C_MUX_IO_ADDR 0x24
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#define I2C_MUX_IO2_ADDR 0x25
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#define I2C_MUX_IO_0 0
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#define I2C_MUX_IO_1 1
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#define SW_BOOT_MASK 0x03
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#define SW_BOOT_EMU 0x02
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#define SW_BOOT_BANK1 0x00
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#define SW_BOOT_BANK2 0x01
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#define SW_REV_MASK 0xF8
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#define SW_REV_A 0xF8
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#define SW_REV_B 0xF0
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#define SW_REV_C 0xE8
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#define SW_REV_C1 0xE0
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#define SW_REV_C2 0xD8
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#define SW_REV_D 0xD0
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#define SW_REV_E 0xC8
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#define __PHY_MASK 0xF9
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#define __PHY_ETH2_MASK 0xFB
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#define __PHY_ETH1_MASK 0xFD
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/* MMC */
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#ifdef CONFIG_MMC
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#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
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#endif
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#define CONFIG_PCIE1 /* PCIE controller 1 */
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#define CONFIG_PCI_SCAN_SHOW
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#define CONFIG_CMD_MEMINFO
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#undef CONFIG_EXTRA_ENV_SETTINGS
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"verify=no\0" \
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"fdt_high=0xffffffffffffffff\0" \
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"initrd_high=0xffffffffffffffff\0" \
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"fdt_addr=0x00f00000\0" \
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"kernel_addr=0x01000000\0" \
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"kernelheader_addr=0x600000\0" \
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"scriptaddr=0x80000000\0" \
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"scripthdraddr=0x80080000\0" \
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"fdtheader_addr_r=0x80100000\0" \
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"kernelheader_addr_r=0x80200000\0" \
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"kernel_addr_r=0x96000000\0" \
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"fdt_addr_r=0x90000000\0" \
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"load_addr=0xa0000000\0" \
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"kernel_size=0x2800000\0" \
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"kernelheader_size=0x40000\0" \
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"console=ttyS0,115200\0" \
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BOOTENV \
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"boot_scripts=ls1012ardb_boot.scr\0" \
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"boot_script_hdr=hdr_ls1012ardb_bs.out\0" \
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"scan_dev_for_boot_part=" \
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"part list ${devtype} ${devnum} devplist; " \
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"env exists devplist || setenv devplist 1; " \
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"for distro_bootpart in ${devplist}; do " \
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"if fstype ${devtype} " \
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"${devnum}:${distro_bootpart} " \
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"bootfstype; then " \
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"run scan_dev_for_boot; " \
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"fi; " \
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"done\0" \
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"scan_dev_for_boot=" \
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"echo Scanning ${devtype} " \
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"${devnum}:${distro_bootpart}...; " \
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"for prefix in ${boot_prefixes}; do " \
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"run scan_dev_for_scripts; " \
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"done;" \
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"\0" \
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"boot_a_script=" \
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"load ${devtype} ${devnum}:${distro_bootpart} " \
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"${scriptaddr} ${prefix}${script}; " \
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"env exists secureboot && load ${devtype} " \
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"${devnum}:${distro_bootpart} " \
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"${scripthdraddr} ${prefix}${boot_script_hdr}; " \
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"env exists secureboot " \
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"&& esbc_validate ${scripthdraddr};" \
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"source ${scriptaddr}\0" \
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"installer=load mmc 0:2 $load_addr " \
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"/flex_installer_arm64.itb; " \
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"bootm $load_addr#$board\0" \
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"qspi_bootcmd=pfe stop; echo Trying load from qspi..;" \
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"sf probe && sf read $load_addr " \
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"$kernel_addr $kernel_size; env exists secureboot " \
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"&& sf read $kernelheader_addr_r $kernelheader_addr " \
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"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
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"bootm $load_addr#$board\0"
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#undef CONFIG_BOOTCOMMAND
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#ifdef CONFIG_TFABOOT
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#undef QSPI_NOR_BOOTCOMMAND
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#define QSPI_NOR_BOOTCOMMAND "pfe stop; run distro_bootcmd; run qspi_bootcmd; "\
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"env exists secureboot && esbc_halt;"
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#else
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#define CONFIG_BOOTCOMMAND "pfe stop; run distro_bootcmd; run qspi_bootcmd; "\
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"env exists secureboot && esbc_halt;"
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#endif
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#include <asm/fsl_secure_boot.h>
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#endif /* __LS1012ARDB_H__ */
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