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![Stefan Roese](/assets/img/avatar_default.png)
This patch adds support for programming of the StratixV FPGAs. Programming is done in this case (board theadorable) via SPI. The board may provide board specific code for bitstream programming. This StratixV support will be used by the theadorable board. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Tom Rini <trini@konsulko.com> Signed-off-by: Stefan Roese <sr@denx.de>
177 lines
4.2 KiB
C
177 lines
4.2 KiB
C
/*
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* (C) Copyright 2003
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* Steven Scholz, imc Measurement & Control, steven.scholz@imc-berlin.de
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*
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* (C) Copyright 2002
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* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* Altera FPGA support
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*/
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#include <common.h>
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#include <errno.h>
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#include <ACEX1K.h>
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#include <stratixII.h>
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/* Define FPGA_DEBUG to 1 to get debug printf's */
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#define FPGA_DEBUG 0
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static const struct altera_fpga {
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enum altera_family family;
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const char *name;
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int (*load)(Altera_desc *, const void *, size_t);
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int (*dump)(Altera_desc *, const void *, size_t);
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int (*info)(Altera_desc *);
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} altera_fpga[] = {
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#if defined(CONFIG_FPGA_ACEX1K)
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{ Altera_ACEX1K, "ACEX1K", ACEX1K_load, ACEX1K_dump, ACEX1K_info },
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{ Altera_CYC2, "ACEX1K", ACEX1K_load, ACEX1K_dump, ACEX1K_info },
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#elif defined(CONFIG_FPGA_CYCLON2)
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{ Altera_ACEX1K, "CycloneII", CYC2_load, CYC2_dump, CYC2_info },
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{ Altera_CYC2, "CycloneII", CYC2_load, CYC2_dump, CYC2_info },
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#endif
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#if defined(CONFIG_FPGA_STRATIX_II)
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{ Altera_StratixII, "StratixII", StratixII_load,
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StratixII_dump, StratixII_info },
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#endif
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#if defined(CONFIG_FPGA_STRATIX_V)
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{ Altera_StratixV, "StratixV", stratixv_load, NULL, NULL },
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#endif
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#if defined(CONFIG_FPGA_SOCFPGA)
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{ Altera_SoCFPGA, "SoC FPGA", socfpga_load, NULL, NULL },
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#endif
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};
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static int altera_validate(Altera_desc *desc, const char *fn)
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{
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if (!desc) {
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printf("%s: NULL descriptor!\n", fn);
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return -EINVAL;
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}
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if ((desc->family < min_altera_type) ||
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(desc->family > max_altera_type)) {
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printf("%s: Invalid family type, %d\n", fn, desc->family);
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return -EINVAL;
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}
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if ((desc->iface < min_altera_iface_type) ||
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(desc->iface > max_altera_iface_type)) {
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printf("%s: Invalid Interface type, %d\n", fn, desc->iface);
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return -EINVAL;
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}
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if (!desc->size) {
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printf("%s: NULL part size\n", fn);
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return -EINVAL;
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}
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return 0;
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}
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static const struct altera_fpga *
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altera_desc_to_fpga(Altera_desc *desc, const char *fn)
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{
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int i;
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if (altera_validate(desc, fn)) {
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printf("%s: Invalid device descriptor\n", fn);
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return NULL;
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}
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for (i = 0; i < ARRAY_SIZE(altera_fpga); i++) {
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if (desc->family == altera_fpga[i].family)
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break;
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}
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if (i == ARRAY_SIZE(altera_fpga)) {
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printf("%s: Unsupported family type, %d\n", fn, desc->family);
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return NULL;
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}
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return &altera_fpga[i];
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}
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int altera_load(Altera_desc *desc, const void *buf, size_t bsize)
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{
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const struct altera_fpga *fpga = altera_desc_to_fpga(desc, __func__);
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if (!fpga)
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return FPGA_FAIL;
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debug_cond(FPGA_DEBUG, "%s: Launching the %s Loader...\n",
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__func__, fpga->name);
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if (fpga->load)
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return fpga->load(desc, buf, bsize);
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return 0;
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}
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int altera_dump(Altera_desc *desc, const void *buf, size_t bsize)
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{
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const struct altera_fpga *fpga = altera_desc_to_fpga(desc, __func__);
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if (!fpga)
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return FPGA_FAIL;
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debug_cond(FPGA_DEBUG, "%s: Launching the %s Reader...\n",
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__func__, fpga->name);
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if (fpga->dump)
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return fpga->dump(desc, buf, bsize);
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return 0;
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}
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int altera_info(Altera_desc *desc)
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{
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const struct altera_fpga *fpga = altera_desc_to_fpga(desc, __func__);
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if (!fpga)
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return FPGA_FAIL;
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printf("Family: \t%s\n", fpga->name);
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printf("Interface type:\t");
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switch (desc->iface) {
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case passive_serial:
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printf("Passive Serial (PS)\n");
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break;
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case passive_parallel_synchronous:
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printf("Passive Parallel Synchronous (PPS)\n");
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break;
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case passive_parallel_asynchronous:
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printf("Passive Parallel Asynchronous (PPA)\n");
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break;
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case passive_serial_asynchronous:
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printf("Passive Serial Asynchronous (PSA)\n");
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break;
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case altera_jtag_mode: /* Not used */
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printf("JTAG Mode\n");
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break;
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case fast_passive_parallel:
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printf("Fast Passive Parallel (FPP)\n");
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break;
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case fast_passive_parallel_security:
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printf("Fast Passive Parallel with Security (FPPS)\n");
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break;
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/* Add new interface types here */
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default:
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printf("Unsupported interface type, %d\n", desc->iface);
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}
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printf("Device Size: \t%zd bytes\n"
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"Cookie: \t0x%x (%d)\n",
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desc->size, desc->cookie, desc->cookie);
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if (desc->iface_fns) {
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printf("Device Function Table @ 0x%p\n", desc->iface_fns);
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if (fpga->info)
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fpga->info(desc);
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} else {
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printf("No Device Function Table.\n");
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}
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return FPGA_SUCCESS;
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}
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