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c91e4b8b08
The IMX6 MMDC calibration registers depend on propagation delay and capacitive loading between the SoC's MMDC and the DDR3 chips. On the Ventana boards the board layout varies little in trace-lengths such that propagation delays are irrelevant thus we can simply things by using calibration values obtained from various board layouts based on a common SoC and DDR chip configuration. This eliminates board-model from being needed allowing more flexibility. These values were tested on a large sample size of Gateworks Ventana boards ranging in layout, and memory configuration over the entire temperature range supported. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
449 lines
13 KiB
C
449 lines
13 KiB
C
/*
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* Copyright (C) 2014 Gateworks Corporation
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* Author: Tim Harvey <tharvey@gateworks.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <i2c.h>
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#include <asm/io.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/mx6-ddr.h>
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#include <asm/arch/mx6-pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/imx-common/boot_mode.h>
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#include <asm/imx-common/iomux-v3.h>
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#include <asm/imx-common/mxc_i2c.h>
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#include <spl.h>
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#include "ventana_eeprom.h"
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DECLARE_GLOBAL_DATA_PTR;
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#define RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */
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#define I2C_GSC 0
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#define GSC_EEPROM_ADDR 0x51
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#define GSC_EEPROM_DDR_SIZE 0x2B /* enum (512,1024,2048) MB */
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#define GSC_EEPROM_DDR_WIDTH 0x2D /* enum (32,64) bit */
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#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
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PAD_CTL_ODE | PAD_CTL_SRE_FAST)
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#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
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#define CONFIG_SYS_I2C_SPEED 100000
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/* I2C1: GSC */
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static struct i2c_pads_info mx6q_i2c_pad_info0 = {
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.scl = {
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.i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC,
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.gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC,
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.gp = IMX_GPIO_NR(3, 21)
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},
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.sda = {
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.i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC,
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.gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC,
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.gp = IMX_GPIO_NR(3, 28)
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}
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};
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static struct i2c_pads_info mx6dl_i2c_pad_info0 = {
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.scl = {
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.i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC,
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.gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC,
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.gp = IMX_GPIO_NR(3, 21)
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},
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.sda = {
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.i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC,
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.gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC,
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.gp = IMX_GPIO_NR(3, 28)
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}
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};
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static void i2c_setup_iomux(void)
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{
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if (is_cpu_type(MXC_CPU_MX6Q))
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setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info0);
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else
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setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info0);
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}
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/* configure MX6Q/DUAL mmdc DDR io registers */
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struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
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/* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
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.dram_sdclk_0 = 0x00020030,
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.dram_sdclk_1 = 0x00020030,
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.dram_cas = 0x00020030,
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.dram_ras = 0x00020030,
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.dram_reset = 0x00020030,
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/* SDCKE[0:1]: 100k pull-up */
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.dram_sdcke0 = 0x00003000,
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.dram_sdcke1 = 0x00003000,
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/* SDBA2: pull-up disabled */
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.dram_sdba2 = 0x00000000,
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/* SDODT[0:1]: 100k pull-up, 40 ohm */
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.dram_sdodt0 = 0x00003030,
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.dram_sdodt1 = 0x00003030,
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/* SDQS[0:7]: Differential input, 40 ohm */
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.dram_sdqs0 = 0x00000030,
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.dram_sdqs1 = 0x00000030,
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.dram_sdqs2 = 0x00000030,
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.dram_sdqs3 = 0x00000030,
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.dram_sdqs4 = 0x00000030,
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.dram_sdqs5 = 0x00000030,
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.dram_sdqs6 = 0x00000030,
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.dram_sdqs7 = 0x00000030,
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/* DQM[0:7]: Differential input, 40 ohm */
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.dram_dqm0 = 0x00020030,
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.dram_dqm1 = 0x00020030,
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.dram_dqm2 = 0x00020030,
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.dram_dqm3 = 0x00020030,
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.dram_dqm4 = 0x00020030,
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.dram_dqm5 = 0x00020030,
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.dram_dqm6 = 0x00020030,
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.dram_dqm7 = 0x00020030,
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};
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/* configure MX6Q/DUAL mmdc GRP io registers */
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struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
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/* DDR3 */
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.grp_ddr_type = 0x000c0000,
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.grp_ddrmode_ctl = 0x00020000,
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/* disable DDR pullups */
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.grp_ddrpke = 0x00000000,
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/* ADDR[00:16], SDBA[0:1]: 40 ohm */
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.grp_addds = 0x00000030,
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/* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
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.grp_ctlds = 0x00000030,
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/* DATA[00:63]: Differential input, 40 ohm */
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.grp_ddrmode = 0x00020000,
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.grp_b0ds = 0x00000030,
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.grp_b1ds = 0x00000030,
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.grp_b2ds = 0x00000030,
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.grp_b3ds = 0x00000030,
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.grp_b4ds = 0x00000030,
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.grp_b5ds = 0x00000030,
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.grp_b6ds = 0x00000030,
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.grp_b7ds = 0x00000030,
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};
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/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
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struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
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/* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
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.dram_sdclk_0 = 0x00020030,
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.dram_sdclk_1 = 0x00020030,
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.dram_cas = 0x00020030,
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.dram_ras = 0x00020030,
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.dram_reset = 0x00020030,
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/* SDCKE[0:1]: 100k pull-up */
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.dram_sdcke0 = 0x00003000,
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.dram_sdcke1 = 0x00003000,
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/* SDBA2: pull-up disabled */
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.dram_sdba2 = 0x00000000,
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/* SDODT[0:1]: 100k pull-up, 40 ohm */
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.dram_sdodt0 = 0x00003030,
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.dram_sdodt1 = 0x00003030,
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/* SDQS[0:7]: Differential input, 40 ohm */
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.dram_sdqs0 = 0x00000030,
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.dram_sdqs1 = 0x00000030,
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.dram_sdqs2 = 0x00000030,
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.dram_sdqs3 = 0x00000030,
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.dram_sdqs4 = 0x00000030,
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.dram_sdqs5 = 0x00000030,
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.dram_sdqs6 = 0x00000030,
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.dram_sdqs7 = 0x00000030,
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/* DQM[0:7]: Differential input, 40 ohm */
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.dram_dqm0 = 0x00020030,
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.dram_dqm1 = 0x00020030,
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.dram_dqm2 = 0x00020030,
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.dram_dqm3 = 0x00020030,
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.dram_dqm4 = 0x00020030,
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.dram_dqm5 = 0x00020030,
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.dram_dqm6 = 0x00020030,
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.dram_dqm7 = 0x00020030,
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};
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/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
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struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
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/* DDR3 */
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.grp_ddr_type = 0x000c0000,
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/* SDQS[0:7]: Differential input, 40 ohm */
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.grp_ddrmode_ctl = 0x00020000,
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/* disable DDR pullups */
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.grp_ddrpke = 0x00000000,
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/* ADDR[00:16], SDBA[0:1]: 40 ohm */
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.grp_addds = 0x00000030,
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/* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
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.grp_ctlds = 0x00000030,
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/* DATA[00:63]: Differential input, 40 ohm */
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.grp_ddrmode = 0x00020000,
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.grp_b0ds = 0x00000030,
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.grp_b1ds = 0x00000030,
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.grp_b2ds = 0x00000030,
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.grp_b3ds = 0x00000030,
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.grp_b4ds = 0x00000030,
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.grp_b5ds = 0x00000030,
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.grp_b6ds = 0x00000030,
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.grp_b7ds = 0x00000030,
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};
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/* MT41K128M16JT-125 */
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static struct mx6_ddr3_cfg mt41k128m16jt_125 = {
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.mem_speed = 1600,
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.density = 2,
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.width = 16,
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.banks = 8,
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.rowaddr = 14,
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.coladdr = 10,
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.pagesz = 2,
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.trcd = 1375,
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.trcmin = 4875,
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.trasmin = 3500,
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};
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/* MT41K256M16HA-125 */
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static struct mx6_ddr3_cfg mt41k256m16ha_125 = {
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.mem_speed = 1600,
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.density = 4,
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.width = 16,
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.banks = 8,
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.rowaddr = 15,
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.coladdr = 10,
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.pagesz = 2,
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.trcd = 1375,
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.trcmin = 4875,
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.trasmin = 3500,
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};
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/*
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* calibration - these are the various CPU/DDR3 combinations we support
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*/
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static struct mx6_mmdc_calibration mx6dq_128x32_mmdc_calib = {
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/* write leveling calibration determine */
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.p0_mpwldectrl0 = 0x00190017,
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.p0_mpwldectrl1 = 0x00140026,
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/* Read DQS Gating calibration */
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.p0_mpdgctrl0 = 0x43380347,
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.p0_mpdgctrl1 = 0x433C034D,
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/* Read Calibration: DQS delay relative to DQ read access */
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.p0_mprddlctl = 0x3C313539,
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/* Write Calibration: DQ/DM delay relative to DQS write access */
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.p0_mpwrdlctl = 0x36393C39,
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};
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static struct mx6_mmdc_calibration mx6sdl_128x32_mmdc_calib = {
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/* write leveling calibration determine */
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.p0_mpwldectrl0 = 0x003C003C,
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.p0_mpwldectrl1 = 0x001F002A,
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/* Read DQS Gating calibration */
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.p0_mpdgctrl0 = 0x42410244,
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.p0_mpdgctrl1 = 0x4234023A,
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/* Read Calibration: DQS delay relative to DQ read access */
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.p0_mprddlctl = 0x484A4C4B,
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/* Write Calibration: DQ/DM delay relative to DQS write access */
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.p0_mpwrdlctl = 0x33342B32,
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};
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static struct mx6_mmdc_calibration mx6dq_128x64_mmdc_calib = {
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/* write leveling calibration determine */
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.p0_mpwldectrl0 = 0x00190017,
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.p0_mpwldectrl1 = 0x00140026,
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.p1_mpwldectrl0 = 0x0021001C,
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.p1_mpwldectrl1 = 0x0011001D,
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/* Read DQS Gating calibration */
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.p0_mpdgctrl0 = 0x43380347,
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.p0_mpdgctrl1 = 0x433C034D,
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.p1_mpdgctrl0 = 0x032C0324,
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.p1_mpdgctrl1 = 0x03310232,
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/* Read Calibration: DQS delay relative to DQ read access */
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.p0_mprddlctl = 0x3C313539,
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.p1_mprddlctl = 0x37343141,
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/* Write Calibration: DQ/DM delay relative to DQS write access */
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.p0_mpwrdlctl = 0x36393C39,
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.p1_mpwrdlctl = 0x42344438,
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};
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static struct mx6_mmdc_calibration mx6sdl_128x64_mmdc_calib = {
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/* write leveling calibration determine */
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.p0_mpwldectrl0 = 0x003C003C,
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.p0_mpwldectrl1 = 0x001F002A,
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.p1_mpwldectrl0 = 0x00330038,
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.p1_mpwldectrl1 = 0x0022003F,
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/* Read DQS Gating calibration */
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.p0_mpdgctrl0 = 0x42410244,
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.p0_mpdgctrl1 = 0x4234023A,
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.p1_mpdgctrl0 = 0x022D022D,
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.p1_mpdgctrl1 = 0x021C0228,
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/* Read Calibration: DQS delay relative to DQ read access */
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.p0_mprddlctl = 0x484A4C4B,
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.p1_mprddlctl = 0x4B4D4E4B,
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/* Write Calibration: DQ/DM delay relative to DQS write access */
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.p0_mpwrdlctl = 0x33342B32,
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.p1_mpwrdlctl = 0x3933332B,
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};
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static struct mx6_mmdc_calibration mx6dq_256x32_mmdc_calib = {
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/* write leveling calibration determine */
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.p0_mpwldectrl0 = 0x001E001A,
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.p0_mpwldectrl1 = 0x0026001F,
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/* Read DQS Gating calibration */
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.p0_mpdgctrl0 = 0x43370349,
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.p0_mpdgctrl1 = 0x032D0327,
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/* Read Calibration: DQS delay relative to DQ read access */
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.p0_mprddlctl = 0x3D303639,
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/* Write Calibration: DQ/DM delay relative to DQS write access */
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.p0_mpwrdlctl = 0x32363934,
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};
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static struct mx6_mmdc_calibration mx6dq_256x64_mmdc_calib = {
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/* write leveling calibration determine */
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.p0_mpwldectrl0 = 0X00220021,
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.p0_mpwldectrl1 = 0X00200030,
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.p1_mpwldectrl0 = 0X002D0027,
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.p1_mpwldectrl1 = 0X00150026,
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/* Read DQS Gating calibration */
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.p0_mpdgctrl0 = 0x43330342,
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.p0_mpdgctrl1 = 0x0339034A,
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.p1_mpdgctrl0 = 0x032F0325,
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.p1_mpdgctrl1 = 0x032F022E,
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/* Read Calibration: DQS delay relative to DQ read access */
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.p0_mprddlctl = 0X3A2E3437,
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.p1_mprddlctl = 0X35312F3F,
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/* Write Calibration: DQ/DM delay relative to DQS write access */
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.p0_mpwrdlctl = 0X33363B37,
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.p1_mpwrdlctl = 0X40304239,
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};
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static void spl_dram_init(int width, int size_mb, int board_model)
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{
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struct mx6_ddr3_cfg *mem = NULL;
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struct mx6_mmdc_calibration *calib = NULL;
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struct mx6_ddr_sysinfo sysinfo = {
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/* width of data bus:0=16,1=32,2=64 */
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.dsize = width/32,
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/* config for full 4GB range so that get_mem_size() works */
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.cs_density = 32, /* 32Gb per CS */
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/* single chip select */
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.ncs = 1,
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.cs1_mirror = 0,
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.rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
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#ifdef RTT_NOM_120OHM
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.rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */
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#else
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.rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */
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#endif
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.walat = 1, /* Write additional latency */
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.ralat = 5, /* Read additional latency */
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.mif3_mode = 3, /* Command prediction working mode */
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.bi_on = 1, /* Bank interleaving enabled */
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.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
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.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
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};
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/*
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* MMDC Calibration requires the following data:
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* mx6_mmdc_calibration - board-specific calibration (routing delays)
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* these calibration values depend on board routing, SoC, and DDR
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* mx6_ddr_sysinfo - board-specific memory architecture (width/cs/etc)
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* mx6_ddr_cfg - chip specific timing/layout details
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*/
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if (width == 32 && size_mb == 512) {
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mem = &mt41k128m16jt_125;
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if (is_cpu_type(MXC_CPU_MX6Q))
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calib = &mx6dq_128x32_mmdc_calib;
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else
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calib = &mx6sdl_128x32_mmdc_calib;
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debug("2gB density\n");
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} else if (width == 64 && size_mb == 1024) {
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mem = &mt41k128m16jt_125;
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if (is_cpu_type(MXC_CPU_MX6Q))
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calib = &mx6dq_128x64_mmdc_calib;
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else
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calib = &mx6sdl_128x64_mmdc_calib;
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debug("2gB density\n");
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} else if (width == 32 && size_mb == 1024) {
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mem = &mt41k256m16ha_125;
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if (is_cpu_type(MXC_CPU_MX6Q))
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calib = &mx6dq_256x32_mmdc_calib;
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debug("4gB density\n");
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} else if (width == 64 && size_mb == 2048) {
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mem = &mt41k256m16ha_125;
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if (is_cpu_type(MXC_CPU_MX6Q))
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calib = &mx6dq_256x64_mmdc_calib;
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debug("4gB density\n");
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}
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if (!mem) {
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puts("Error: Invalid Memory Configuration\n");
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hang();
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}
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if (!calib) {
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puts("Error: Invalid Board Calibration Configuration\n");
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hang();
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}
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if (is_cpu_type(MXC_CPU_MX6Q))
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mx6dq_dram_iocfg(width, &mx6dq_ddr_ioregs,
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&mx6dq_grp_ioregs);
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else
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mx6sdl_dram_iocfg(width, &mx6sdl_ddr_ioregs,
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&mx6sdl_grp_ioregs);
|
|
mx6_dram_cfg(&sysinfo, calib, mem);
|
|
}
|
|
|
|
/*
|
|
* called from C runtime startup code (arch/arm/lib/crt0.S:_main)
|
|
* - we have a stack and a place to store GD, both in SRAM
|
|
* - no variable global data is available
|
|
*/
|
|
void board_init_f(ulong dummy)
|
|
{
|
|
struct ventana_board_info ventana_info;
|
|
int board_model;
|
|
|
|
/*
|
|
* Zero out global data:
|
|
* - this shoudl be done by crt0.S
|
|
* - failure to zero it will cause i2c_setup to fail
|
|
*/
|
|
memset((void *)gd, 0, sizeof(struct global_data));
|
|
|
|
/* setup AIPS and disable watchdog */
|
|
arch_cpu_init();
|
|
|
|
/* iomux and setup of i2c */
|
|
board_early_init_f();
|
|
i2c_setup_iomux();
|
|
|
|
/* setup GP timer */
|
|
timer_init();
|
|
|
|
/* UART clocks enabled and gd valid - init serial console */
|
|
preloader_console_init();
|
|
|
|
/* read/validate EEPROM info to determine board model and SDRAM cfg */
|
|
board_model = read_eeprom(I2C_GSC, &ventana_info);
|
|
|
|
/* provide some some default: 32bit 128MB */
|
|
if (GW_UNKNOWN == board_model) {
|
|
ventana_info.sdram_width = 2;
|
|
ventana_info.sdram_size = 3;
|
|
}
|
|
|
|
/* configure MMDC for SDRAM width/size and per-model calibration */
|
|
spl_dram_init(8 << ventana_info.sdram_width,
|
|
16 << ventana_info.sdram_size,
|
|
board_model);
|
|
|
|
/* Clear the BSS. */
|
|
memset(__bss_start, 0, __bss_end - __bss_start);
|
|
|
|
/* load/boot image from boot device */
|
|
board_init_r(NULL, 0);
|
|
}
|
|
|
|
void reset_cpu(ulong addr)
|
|
{
|
|
}
|