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https://github.com/brain-hackers/u-boot-brain
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c916d7c914
The Frame Manager (FMan) on QorIQ SoCs with DPAA (datapath acceleration architecture) is the ethernet contoller block. Normally it is utilized via Queue Manager (Qman) and Buffer Manager (Bman). However for boot usage the FMan supports a mode similar to QE or CPM ethernet collers called Independent mode. Additionally the FMan block supports multiple 1g and 10g interfaces as a single entity in the system rather than each controller being managed uniquely. This means we have to initialize all of Fman regardless of the number of interfaces we utilize. Different SoCs support different combinations of the number of FMan as well as the number of 1g & 10g interfaces support per Fman. We add support for the following SoCs: * P1023 - 1 Fman, 2x1g * P4080 - 2 Fman, each Fman has 4x1g and 1x10g * P204x/P3041/P5020 - 1 Fman, 5x1g, 1x10g Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Dai Haruki <dai.haruki@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Ioana Radulescu <ruxandra.radulescu@freescale.com> Signed-off-by: Lei Xu <B33228@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Shaohui Xie <b21989@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
69 lines
2.0 KiB
C
69 lines
2.0 KiB
C
/*
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* Copyright 2011 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <phy.h>
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#include <fm_eth.h>
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#include <asm/io.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_serdes.h>
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u32 port_to_devdisr[] = {
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[FM1_DTSEC1] = MPC85xx_DEVDISR_TSEC1,
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[FM1_DTSEC2] = MPC85xx_DEVDISR_TSEC2,
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};
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static int is_device_disabled(enum fm_port port)
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{
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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u32 devdisr = in_be32(&gur->devdisr);
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return port_to_devdisr[port] & devdisr;
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}
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phy_interface_t fman_port_enet_if(enum fm_port port)
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{
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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u32 pordevsr = in_be32(&gur->pordevsr);
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if (is_device_disabled(port))
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return PHY_INTERFACE_MODE_NONE;
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/* DTSEC1 can be SGMII, RGMII or RMII */
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if (port == FM1_DTSEC1) {
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if (is_serdes_configured(SGMII_FM1_DTSEC1))
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return PHY_INTERFACE_MODE_SGMII;
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if (pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS) {
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if (pordevsr & MPC85xx_PORDEVSR_TSEC1_PRTC)
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return PHY_INTERFACE_MODE_RGMII;
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else
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return PHY_INTERFACE_MODE_RMII;
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}
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}
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/* DTSEC2 only supports SGMII or RGMII */
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if (port == FM1_DTSEC2) {
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if (is_serdes_configured(SGMII_FM1_DTSEC2))
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return PHY_INTERFACE_MODE_SGMII;
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if (pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)
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return PHY_INTERFACE_MODE_RGMII;
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}
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return PHY_INTERFACE_MODE_NONE;
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}
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