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c14f3c3111
AM654 SoC is IO coherent wrt A53 cores, therefore enable SYS_DISABLE_DCACHE_OPS to avoid cache operations in A53 SPL/U-Boot. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
54 lines
918 B
Plaintext
54 lines
918 B
Plaintext
# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
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# Lokesh Vutla <lokeshvutla@ti.com>
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choice
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prompt "K3 AM65 based boards"
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optional
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config TARGET_AM654_A53_EVM
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bool "TI K3 based AM654 EVM running on A53"
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select ARM64
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select SOC_K3_AM6
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select SYS_DISABLE_DCACHE_OPS
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config TARGET_AM654_R5_EVM
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bool "TI K3 based AM654 EVM running on R5"
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select CPU_V7R
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select SYS_THUMB_BUILD
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select SOC_K3_AM6
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select K3_AM654_DDRSS
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imply SYS_K3_SPL_ATF
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endchoice
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if TARGET_AM654_A53_EVM
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config SYS_BOARD
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default "am65x"
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config SYS_VENDOR
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default "ti"
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config SYS_CONFIG_NAME
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default "am65x_evm"
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endif
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if TARGET_AM654_R5_EVM
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config SYS_BOARD
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default "am65x"
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config SYS_VENDOR
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default "ti"
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config SYS_CONFIG_NAME
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default "am65x_evm"
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config SPL_LDSCRIPT
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default "arch/arm/mach-omap2/u-boot-spl.lds"
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endif
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