mirror of
https://github.com/brain-hackers/u-boot-brain
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c8381bf435
The controller's Reed-Solomon ECC hardware is used except of course for raw reads and writes. It covers in- and out-of-band data together. The SPL framework is supported. Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
53 lines
1.2 KiB
C
53 lines
1.2 KiB
C
/*
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* Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/uart.h>
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#include <asm/io.h>
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static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
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static struct uart_ctrl_regs *ctrl = (struct uart_ctrl_regs *)UART_CTRL_BASE;
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void lpc32xx_uart_init(unsigned int uart_id)
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{
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if (uart_id < 1 || uart_id > 7)
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return;
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/* Disable loopback mode, if it is set by S1L bootloader */
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clrbits_le32(&ctrl->loop,
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UART_LOOPBACK(CONFIG_SYS_LPC32XX_UART));
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if (uart_id < 3 || uart_id > 6)
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return;
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/* Enable UART system clock */
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setbits_le32(&clk->uartclk_ctrl, CLK_UART(uart_id));
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/* Set UART into autoclock mode */
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clrsetbits_le32(&ctrl->clkmode,
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UART_CLKMODE_MASK(uart_id),
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UART_CLKMODE_AUTO(uart_id));
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/* Bypass pre-divider of UART clock */
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writel(CLK_UART_X_DIV(1) | CLK_UART_Y_DIV(1),
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&clk->u3clk + (uart_id - 3));
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}
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void lpc32xx_mac_init(void)
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{
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/* Enable MAC interface */
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writel(CLK_MAC_REG | CLK_MAC_SLAVE | CLK_MAC_MASTER
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| CLK_MAC_MII, &clk->macclk_ctrl);
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}
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void lpc32xx_mlc_nand_init(void)
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{
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/* Enable NAND interface */
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writel(CLK_NAND_MLC | CLK_NAND_MLC_INT, &clk->flashclk_ctrl);
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}
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