mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-05 18:56:15 +09:00
1df7f0b6a0
Only a specific type of SPI flash exists on a board, having board Kconfig to select the SPI flash seems to make more sense. Other flash types are not necessary except coreboot, which implies all available flash drivers there. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
43 lines
726 B
Plaintext
43 lines
726 B
Plaintext
if TARGET_CHROMEBOOK_LINK || TARGET_CHROMEBOOK_LINK64
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config SYS_BOARD
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default "chromebook_link"
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config SYS_VENDOR
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default "google"
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config SYS_SOC
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default "ivybridge"
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config SYS_CONFIG_NAME
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default "chromebook_link"
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config SYS_TEXT_BASE
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default 0xfff00000 if !SUPPORT_SPL
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default 0x10000000 if SUPPORT_SPL
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select X86_RESET_VECTOR
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select NORTHBRIDGE_INTEL_IVYBRIDGE
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select HAVE_INTEL_ME
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select BOARD_ROMSIZE_KB_8192
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select SPI_FLASH_WINBOND
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config PCIE_ECAM_BASE
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default 0xf0000000
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config EARLY_POST_CROS_EC
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bool "Enable early post to Chrome OS EC"
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default y
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config SYS_CAR_ADDR
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hex
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default 0xff7e0000
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config SYS_CAR_SIZE
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hex
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default 0x20000
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endif
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