Tom Warren c82014daf5 ARM: tegra: implement MASK_BITS_31_29 ... Some clock sources have 3-bit muxes in bits 31:29. Implement core support for this mux field. Signed-off-by: Tom Warren <twarren@nvidia.com> [swarren, extracted from a larger patch by Tom] Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>		2014-02-03 09:46:45 -07:00
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ap.c	ARM: tegra: accept any SKU ID for most chips	2014-02-03 09:46:44 -07:00
board.c	Add GPL-2.0+ SPDX-License-Identifier to source files	2013-07-24 09:44:38 -04:00
cache.c	Tegra: Configure L2 cache control reg properly.	2013-04-15 11:01:38 -07:00
clock.c	ARM: tegra: implement MASK_BITS_31_29	2014-02-03 09:46:45 -07:00
lowlevel_init.S	Add GPL-2.0+ SPDX-License-Identifier to source files	2013-07-24 09:44:38 -04:00
Makefile	ARM: tegra: convert to common timer code	2013-11-04 11:24:22 -05:00
sys_info.c	Add GPL-2.0+ SPDX-License-Identifier to source files	2013-07-24 09:44:38 -04:00