mirror of
https://github.com/brain-hackers/u-boot-brain
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1f36f73fe7
Use the MMU hardware to set up 1:1 mappings between physical and virtual addresses. This allows us to bypass the cache when accessing the flash without having to do any physical-to-virtual address mapping in the CFI driver. The virtual memory mappings are defined at compile time through a sorted array of virtual memory range objects. When a TLB miss exception happens, the exception handler does a binary search through the array until it finds a matching entry and loads it into the TLB. The u-boot image itself is covered by a fixed TLB entry which is never replaced. This makes the 'saveenv' command work again on ATNGW100 and other boards using the CFI driver, hopefully without breaking any rules. Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
67 lines
2.2 KiB
C
67 lines
2.2 KiB
C
/*
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* In order to deal with the hardcoded u-boot requirement that virtual
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* addresses are always mapped 1:1 with physical addresses, we implement
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* a small virtual memory manager so that we can use the MMU hardware in
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* order to get the caching properties right.
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*
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* A few pages (or possibly just one) are locked in the TLB permanently
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* in order to avoid recursive TLB misses, but most pages are faulted in
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* on demand.
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*/
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#ifndef __ASM_ARCH_MMU_H
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#define __ASM_ARCH_MMU_H
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#include <asm/sysreg.h>
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#define PAGE_SHIFT 20
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#define PAGE_SIZE (1UL << PAGE_SHIFT)
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#define PAGE_ADDR_MASK (~(PAGE_SIZE - 1))
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#define MMU_VMR_CACHE_NONE \
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(SYSREG_BF(AP, 3) | SYSREG_BF(SZ, 3) | SYSREG_BIT(TLBELO_D))
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#define MMU_VMR_CACHE_WBUF \
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(MMU_VMR_CACHE_NONE | SYSREG_BIT(B))
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#define MMU_VMR_CACHE_WRTHRU \
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(MMU_VMR_CACHE_NONE | SYSREG_BIT(TLBELO_C) | SYSREG_BIT(W))
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#define MMU_VMR_CACHE_WRBACK \
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(MMU_VMR_CACHE_WBUF | SYSREG_BIT(TLBELO_C))
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/*
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* This structure is used in our "page table". Instead of the usual
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* x86-inspired radix tree, we let each entry cover an arbitrary-sized
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* virtual address range and store them in a binary search tree. This is
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* somewhat slower, but should use significantly less RAM, and we
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* shouldn't get many TLB misses when using 1 MB pages anyway.
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*
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* With 1 MB pages, we need 12 bits to store the page number. In
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* addition, we stick an Invalid bit in the high bit of virt_pgno (if
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* set, it cannot possibly match any faulting page), and all the bits
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* that need to be written to TLBELO in phys_pgno.
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*/
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struct mmu_vm_range {
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uint16_t virt_pgno;
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uint16_t nr_pages;
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uint32_t phys;
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};
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/*
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* An array of mmu_vm_range objects describing all pageable addresses.
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* The array is sorted by virt_pgno so that the TLB miss exception
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* handler can do a binary search to find the correct entry.
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*/
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extern struct mmu_vm_range mmu_vmr_table[];
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/*
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* Initialize the MMU. This will set up a fixed TLB entry for the static
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* u-boot image at dest_addr and enable paging.
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*/
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void mmu_init_r(unsigned long dest_addr);
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/*
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* Handle a TLB miss exception. This function is called directly from
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* the exception vector table written in assembly.
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*/
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int mmu_handle_tlb_miss(void);
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#endif /* __ASM_ARCH_MMU_H */
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