mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-05 02:36:39 +09:00
e895a4b06f
This function can fail if the device tree runs out of space. Rather than silently booting with an incomplete device tree, allow the failure to be detected. Unfortunately this involves changing a lot of places in the code. I have not changed behvaiour to return an error where one is not currently returned, to avoid unexpected breakage. Eventually it would be nice to allow boards to register functions to be called to update the device tree. This would avoid all the many functions to do this. However it's not clear yet if this should be done using driver model or with a linker list. This work is left for later. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de>
207 lines
4.7 KiB
C
207 lines
4.7 KiB
C
/*
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* vme8349.c -- esd VME8349 board support
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*
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* Copyright (c) 2008-2009 esd gmbh.
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*
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* (C) Copyright 2006
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* Reinhard Arlt <reinhard.arlt@esd-electronics.com>
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* Based on board/mpc8349emds/mpc8349emds.c (and previous 834x releases.)
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <ioports.h>
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#include <mpc83xx.h>
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#include <asm/mpc8349_pci.h>
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#if defined(CONFIG_OF_LIBFDT)
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#include <libfdt.h>
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#endif
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#include <asm/io.h>
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#include <asm/mmu.h>
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#include <spd.h>
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#include <spd_sdram.h>
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#include <i2c.h>
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#include <netdev.h>
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void ddr_enable_ecc(unsigned int dram_size);
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phys_size_t initdram(int board_type)
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{
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volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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u32 msize = 0;
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if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
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return -1;
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/* DDR SDRAM - Main memory */
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im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
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msize = spd_sdram();
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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/*
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* Initialize and enable DDR ECC.
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*/
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ddr_enable_ecc(msize * 1024 * 1024);
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#endif
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/* Now check memory size (after ECC is initialized) */
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msize = get_ram_size(0, msize);
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/* return total bus SDRAM size(bytes) -- DDR */
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return msize * 1024 * 1024;
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}
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int checkboard(void)
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{
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#ifdef VME_CADDY2
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puts("Board: esd VME-CADDY/2\n");
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#else
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puts("Board: esd VME-CPU/8349\n");
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#endif
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return 0;
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}
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#ifdef VME_CADDY2
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int board_eth_init(bd_t *bis)
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{
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return pci_eth_init(bis);
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}
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#endif
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#if defined(CONFIG_OF_BOARD_SETUP)
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int ft_board_setup(void *blob, bd_t *bd)
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{
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ft_cpu_setup(blob, bd);
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#ifdef CONFIG_PCI
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ft_pci_setup(blob, bd);
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#endif
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return 0;
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}
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#endif
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int misc_init_r()
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{
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immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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clrsetbits_be32(&im->im_lbc.lcrr, LBCR_LDIS, 0);
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return 0;
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}
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/*
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* Provide SPD values for spd_sdram(). Both boards (VME-CADDY/2
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* and VME-CADDY/2) have different SDRAM configurations.
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*/
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#ifdef VME_CADDY2
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#define SMALL_RAM 0xff
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#define LARGE_RAM 0x00
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#else
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#define SMALL_RAM 0x00
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#define LARGE_RAM 0xff
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#endif
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#define SPD_VAL(a, b) (((a) & SMALL_RAM) | ((b) & LARGE_RAM))
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static spd_eeprom_t default_spd_eeprom = {
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SPD_VAL(0x80, 0x80), /* 00 use 128 Bytes */
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SPD_VAL(0x07, 0x07), /* 01 use 128 Bytes */
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SPD_MEMTYPE_DDR2, /* 02 type is DDR2 */
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SPD_VAL(0x0d, 0x0d), /* 03 rows: 13 */
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SPD_VAL(0x09, 0x0a), /* 04 cols: 9 / 10 */
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SPD_VAL(0x00, 0x00), /* 05 */
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SPD_VAL(0x40, 0x40), /* 06 */
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SPD_VAL(0x00, 0x00), /* 07 */
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SPD_VAL(0x05, 0x05), /* 08 */
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SPD_VAL(0x30, 0x30), /* 09 */
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SPD_VAL(0x45, 0x45), /* 10 */
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SPD_VAL(0x02, 0x02), /* 11 ecc used */
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SPD_VAL(0x82, 0x82), /* 12 */
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SPD_VAL(0x10, 0x10), /* 13 */
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SPD_VAL(0x08, 0x08), /* 14 */
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SPD_VAL(0x00, 0x00), /* 15 */
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SPD_VAL(0x0c, 0x0c), /* 16 */
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SPD_VAL(0x04, 0x08), /* 17 banks: 4 / 8 */
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SPD_VAL(0x38, 0x38), /* 18 */
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SPD_VAL(0x00, 0x00), /* 19 */
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SPD_VAL(0x02, 0x02), /* 20 */
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SPD_VAL(0x00, 0x00), /* 21 */
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SPD_VAL(0x03, 0x03), /* 22 */
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SPD_VAL(0x3d, 0x3d), /* 23 */
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SPD_VAL(0x45, 0x45), /* 24 */
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SPD_VAL(0x50, 0x50), /* 25 */
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SPD_VAL(0x45, 0x45), /* 26 */
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SPD_VAL(0x3c, 0x3c), /* 27 */
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SPD_VAL(0x28, 0x28), /* 28 */
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SPD_VAL(0x3c, 0x3c), /* 29 */
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SPD_VAL(0x2d, 0x2d), /* 30 */
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SPD_VAL(0x20, 0x80), /* 31 */
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SPD_VAL(0x20, 0x20), /* 32 */
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SPD_VAL(0x27, 0x27), /* 33 */
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SPD_VAL(0x10, 0x10), /* 34 */
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SPD_VAL(0x17, 0x17), /* 35 */
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SPD_VAL(0x3c, 0x3c), /* 36 */
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SPD_VAL(0x1e, 0x1e), /* 37 */
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SPD_VAL(0x1e, 0x1e), /* 38 */
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SPD_VAL(0x00, 0x00), /* 39 */
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SPD_VAL(0x00, 0x06), /* 40 */
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SPD_VAL(0x37, 0x37), /* 41 */
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SPD_VAL(0x4b, 0x7f), /* 42 */
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SPD_VAL(0x80, 0x80), /* 43 */
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SPD_VAL(0x18, 0x18), /* 44 */
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SPD_VAL(0x22, 0x22), /* 45 */
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SPD_VAL(0x00, 0x00), /* 46 */
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
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SPD_VAL(0x10, 0x10), /* 62 */
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SPD_VAL(0x7e, 0x1d), /* 63 */
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{ 'e', 's', 'd', '-', 'g', 'm', 'b', 'h' },
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SPD_VAL(0x00, 0x00), /* 72 */
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#ifdef VME_CADDY2
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{ "vme-caddy/2 ram " }
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#else
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{ "vme-cpu/2 ram " }
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#endif
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};
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int vme8349_read_spd(uchar chip, uint addr, int alen, uchar *buffer, int len)
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{
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int old_bus = i2c_get_bus_num();
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unsigned int l, sum;
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int valid = 0;
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i2c_set_bus_num(0);
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if (i2c_read(chip, addr, alen, buffer, len) == 0)
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if (memcmp(&buffer[64], &default_spd_eeprom.mid[0], 8) == 0) {
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sum = 0;
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for (l = 0; l < 63; l++)
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sum = (sum + buffer[l]) & 0xff;
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if (sum == buffer[63])
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valid = 1;
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else
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printf("Invalid checksum in EEPROM %02x %02x\n",
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sum, buffer[63]);
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}
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if (valid == 0) {
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memcpy(buffer, (void *)&default_spd_eeprom, len);
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sum = 0;
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for (l = 0; l < 63; l++)
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sum = (sum + buffer[l]) & 0xff;
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if (sum != buffer[63])
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printf("Invalid checksum in FLASH %02x %02x\n",
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sum, buffer[63]);
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buffer[63] = sum;
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}
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i2c_set_bus_num(old_bus);
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return 0;
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}
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