mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-07 05:13:21 +09:00
![Harald Seiler](/assets/img/avatar_default.png)
Use DM_ETH instead of legacy networking. Add VIO as a fixed regulator to the relevant device-trees and augment the FEC node with properties for the reset GPIO. It should be noted that the relevant properties for the reset GPIO already exist in the PHY node (reset-gpios, reset-delay-us, reset-post-delay-us) but U-Boot currently ignores those and only supports the bus-level reset properties in the FEC node (phy-reset-gpios, phy-reset-duration, phy-reset-post-delay). Signed-off-by: Harald Seiler <hws@denx.de>
237 lines
4.7 KiB
C
237 lines
4.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* DHCOM DH-iMX6 PDK board support
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*
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* Copyright (C) 2017 Marek Vasut <marex@denx.de>
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*/
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#include <common.h>
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#include <dm.h>
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#include <eeprom.h>
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#include <init.h>
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#include <dm/device-internal.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/mx6-pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/mach-imx/boot_mode.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/mach-imx/sata.h>
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#include <ahci.h>
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#include <dwc_ahsata.h>
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#include <env.h>
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#include <errno.h>
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#include <fsl_esdhc_imx.h>
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#include <fuse.h>
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#include <i2c_eeprom.h>
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#include <mmc.h>
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#include <usb.h>
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#include <usb/ehci-ci.h>
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DECLARE_GLOBAL_DATA_PTR;
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int dram_init(void)
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{
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gd->ram_size = imx_ddr_size();
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return 0;
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}
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/*
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* Do not overwrite the console
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* Use always serial for U-Boot console
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*/
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int overwrite_console(void)
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{
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return 1;
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}
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static int setup_fec_clock(void)
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{
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struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
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/* set gpr1[21] to select anatop clock */
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clrsetbits_le32(&iomuxc_regs->gpr[1], 0x1 << 21, 0x1 << 21);
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return enable_fec_anatop_clock(0, ENET_50MHZ);
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}
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#ifdef CONFIG_USB_EHCI_MX6
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static void setup_usb(void)
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{
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/*
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* Set daisy chain for otg_pin_id on MX6Q.
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* For MX6DL, this bit is reserved.
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*/
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imx_iomux_set_gpr_register(1, 13, 1, 0);
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}
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int board_usb_phy_mode(int port)
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{
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if (port == 1)
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return USB_INIT_HOST;
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else
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return USB_INIT_DEVICE;
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}
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#endif
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static int setup_dhcom_mac_from_fuse(void)
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{
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struct udevice *dev;
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ofnode eeprom;
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unsigned char enetaddr[6];
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int ret;
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ret = eth_env_get_enetaddr("ethaddr", enetaddr);
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if (ret) /* ethaddr is already set */
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return 0;
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imx_get_mac_from_fuse(0, enetaddr);
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if (is_valid_ethaddr(enetaddr)) {
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eth_env_set_enetaddr("ethaddr", enetaddr);
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return 0;
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}
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eeprom = ofnode_path("/soc/aips-bus@2100000/i2c@21a8000/eeprom@50");
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if (!ofnode_valid(eeprom)) {
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printf("Invalid hardware path to EEPROM!\n");
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return -ENODEV;
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}
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ret = uclass_get_device_by_ofnode(UCLASS_I2C_EEPROM, eeprom, &dev);
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if (ret) {
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printf("Cannot find EEPROM!\n");
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return ret;
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}
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ret = i2c_eeprom_read(dev, 0xfa, enetaddr, 0x6);
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if (ret) {
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printf("Error reading configuration EEPROM!\n");
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return ret;
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}
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if (is_valid_ethaddr(enetaddr))
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eth_env_set_enetaddr("ethaddr", enetaddr);
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return 0;
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}
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int board_early_init_f(void)
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{
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#ifdef CONFIG_USB_EHCI_MX6
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setup_usb();
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#endif
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return 0;
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}
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int board_init(void)
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{
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struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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/* address of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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/* Enable eim_slow clocks */
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setbits_le32(&mxc_ccm->CCGR6, 0x1 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET);
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setup_dhcom_mac_from_fuse();
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setup_fec_clock();
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return 0;
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}
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#ifdef CONFIG_CMD_BMODE
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static const struct boot_mode board_boot_modes[] = {
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/* 4 bit bus width */
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{"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
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{"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
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/* 8 bit bus width */
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{"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
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{NULL, 0},
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};
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#endif
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#define HW_CODE_BIT_0 IMX_GPIO_NR(2, 19)
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#define HW_CODE_BIT_1 IMX_GPIO_NR(6, 6)
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#define HW_CODE_BIT_2 IMX_GPIO_NR(2, 16)
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static int board_get_hwcode(void)
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{
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int hw_code;
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gpio_request(HW_CODE_BIT_0, "HW-code-bit-0");
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gpio_request(HW_CODE_BIT_1, "HW-code-bit-1");
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gpio_request(HW_CODE_BIT_2, "HW-code-bit-2");
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gpio_direction_input(HW_CODE_BIT_0);
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gpio_direction_input(HW_CODE_BIT_1);
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gpio_direction_input(HW_CODE_BIT_2);
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/* HW 100 + HW 200 = 00b; HW 300 = 01b */
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hw_code = ((gpio_get_value(HW_CODE_BIT_2) << 2) |
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(gpio_get_value(HW_CODE_BIT_1) << 1) |
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gpio_get_value(HW_CODE_BIT_0)) + 2;
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return hw_code;
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}
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int board_late_init(void)
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{
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u32 hw_code;
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char buf[16];
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hw_code = board_get_hwcode();
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switch (get_cpu_type()) {
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case MXC_CPU_MX6SOLO:
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snprintf(buf, sizeof(buf), "imx6s-dhcom%1d", hw_code);
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break;
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case MXC_CPU_MX6DL:
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snprintf(buf, sizeof(buf), "imx6dl-dhcom%1d", hw_code);
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break;
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case MXC_CPU_MX6D:
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snprintf(buf, sizeof(buf), "imx6d-dhcom%1d", hw_code);
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break;
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case MXC_CPU_MX6Q:
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snprintf(buf, sizeof(buf), "imx6q-dhcom%1d", hw_code);
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break;
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default:
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snprintf(buf, sizeof(buf), "UNKNOWN%1d", hw_code);
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break;
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}
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env_set("dhcom", buf);
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#ifdef CONFIG_CMD_BMODE
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add_board_boot_modes(board_boot_modes);
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#endif
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return 0;
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}
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int checkboard(void)
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{
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puts("Board: DHCOM i.MX6\n");
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return 0;
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}
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#ifdef CONFIG_MULTI_DTB_FIT
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int board_fit_config_name_match(const char *name)
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{
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if (is_mx6dq()) {
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if (!strcmp(name, "imx6q-dhcom-pdk2"))
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return 0;
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} else if (is_mx6sdl()) {
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if (!strcmp(name, "imx6dl-dhcom-pdk2"))
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return 0;
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}
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return -1;
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}
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#endif
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