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https://github.com/brain-hackers/u-boot-brain
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6f0da4972e
AP325RXA is SH7723's reference board. This has SCIF, NOR Flash, Ethernet, USB host, LCDC, SD Host, Camera and other. In this patch, support SCIF, NOR Flash, and Ethernet. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
244 lines
4.7 KiB
ArmAsm
244 lines
4.7 KiB
ArmAsm
/*
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* Copyright (C) 2008 Renesas Solutions Corp.
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* Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
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*
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* board/ap325rxa/lowlevel_init.S
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <version.h>
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#include <asm/processor.h>
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/*
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* Board specific low level init code, called _very_ early in the
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* startup sequence. Relocation to SDRAM has not happened yet, no
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* stack is available, bss section has not been initialised, etc.
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*
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* (Note: As no stack is available, no subroutines can be called...).
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*/
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.global lowlevel_init
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.text
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.align 2
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lowlevel_init:
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mov.l DRVCRA_A, r1
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mov.l DRVCRA_D, r0
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mov.w r0, @r1
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mov.l DRVCRB_A, r1
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mov.l DRVCRB_D, r0
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mov.w r0, @r1
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mov.l RWTCSR_A, r1
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mov.l RWTCSR_D1, r0
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mov.w r0, @r1
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mov.l RWTCNT_A, r1
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mov.l RWTCNT_D, r0
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mov.w r0, @r1
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mov.l RWTCSR_A, r1
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mov.l RWTCSR_D2, r0
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mov.w r0, @r1
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mov.l FRQCR_A, r1
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mov.l FRQCR_D, r0
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mov.l r0, @r1
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mov.l CMNCR_A, r1
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mov.l CMNCR_D, r0
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mov.l r0, @r1
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mov.l CS0BCR_A ,r1
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mov.l CS0BCR_D ,r0
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mov.l r0, @r1
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mov.l CS4BCR_A ,r1
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mov.l CS4BCR_D ,r0
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mov.l r0, @r1
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mov.l CS5ABCR_A ,r1
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mov.l CS5ABCR_D ,r0
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mov.l r0, @r1
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mov.l CS5BBCR_A ,r1
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mov.l CS5BBCR_D ,r0
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mov.l r0, @r1
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mov.l CS6ABCR_A ,r1
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mov.l CS6ABCR_D ,r0
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mov.l r0, @r1
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mov.l CS6BBCR_A ,r1
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mov.l CS6BBCR_D ,r0
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mov.l r0, @r1
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mov.l CS0WCR_A ,r1
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mov.l CS0WCR_D ,r0
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mov.l r0, @r1
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mov.l CS4WCR_A ,r1
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mov.l CS4WCR_D ,r0
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mov.l r0, @r1
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mov.l CS5AWCR_A ,r1
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mov.l CS5AWCR_D ,r0
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mov.l r0, @r1
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mov.l CS5BWCR_A ,r1
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mov.l CS5BWCR_D ,r0
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mov.l r0, @r1
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mov.l CS6AWCR_A ,r1
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mov.l CS6AWCR_D ,r0
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mov.l r0, @r1
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mov.l CS6BWCR_A ,r1
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mov.l CS6BWCR_D ,r0
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mov.l r0, @r1
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mov.l SBSC_SDCR_A, r1
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mov.l SBSC_SDCR_D1, r0
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mov.l r0, @r1
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mov.l SBSC_SDWCR_A, r1
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mov.l SBSC_SDWCR_D, r0
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mov.l r0, @r1
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mov.l SBSC_SDPCR_A, r1
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mov.l SBSC_SDPCR_D, r0
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mov.l r0, @r1
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mov.l SBSC_RTCSR_A, r1
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mov.l SBSC_RTCSR_D, r0
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mov.l r0, @r1
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mov.l SBSC_RTCNT_A, r1
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mov.l SBSC_RTCNT_D, r0
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mov.l r0, @r1
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mov.l SBSC_RTCOR_A, r1
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mov.l SBSC_RTCOR_D, r0
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mov.l r0, @r1
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mov.l SBSC_SDMR3_A1, r1
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mov.l SBSC_SDMR3_D, r0
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mov.b r0, @r1
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mov.l SBSC_SDMR3_A2, r1
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mov.l SBSC_SDMR3_D, r0
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mov.b r0, @r1
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mov.l SLEEP_CNT, r1
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2: tst r1, r1
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nop
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bf/s 2b
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dt r1
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mov.l SBSC_SDMR3_A3, r1
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mov.l SBSC_SDMR3_D, r0
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mov.b r0, @r1
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mov.l SBSC_SDCR_A, r1
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mov.l SBSC_SDCR_D2, r0
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mov.l r0, @r1
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mov.l CCR_A, r1
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mov.l CCR_D, r0
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mov.l r0, @r1
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! BL bit off (init = ON) (?!?)
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stc sr, r0 ! BL bit off(init=ON)
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mov.l SR_MASK_D, r1
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and r1, r0
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ldc r0, sr
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rts
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mov #0, r0
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.align 2
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DRVCRA_A: .long DRVCRA
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DRVCRB_A: .long DRVCRB
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DRVCRA_D: .long 0x4555
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DRVCRB_D: .long 0x0005
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RWTCSR_A: .long RWTCSR
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RWTCNT_A: .long RWTCNT
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FRQCR_A: .long FRQCR
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RWTCSR_D1: .long 0xa507
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RWTCSR_D2: .long 0xa504
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RWTCNT_D: .long 0x5a00
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FRQCR_D: .long 0x0b04474a
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SBSC_SDCR_A: .long SBSC_SDCR
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SBSC_SDWCR_A: .long SBSC_SDWCR
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SBSC_SDPCR_A: .long SBSC_SDPCR
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SBSC_RTCSR_A: .long SBSC_RTCSR
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SBSC_RTCNT_A: .long SBSC_RTCNT
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SBSC_RTCOR_A: .long SBSC_RTCOR
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SBSC_SDMR3_A1: .long 0xfe510000
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SBSC_SDMR3_A2: .long 0xfe500242
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SBSC_SDMR3_A3: .long 0xfe5c0042
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SBSC_SDCR_D1: .long 0x92810112
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SBSC_SDCR_D2: .long 0x92810912
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SBSC_SDWCR_D: .long 0x05162482
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SBSC_SDPCR_D: .long 0x00300087
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SBSC_RTCSR_D: .long 0xa55a0212
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SBSC_RTCNT_D: .long 0xa55a0000
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SBSC_RTCOR_D: .long 0xa55a0040
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SBSC_SDMR3_D: .long 0x00
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CMNCR_A: .long CMNCR
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CS0BCR_A: .long CS0BCR
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CS4BCR_A: .long CS4BCR
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CS5ABCR_A: .long CS5ABCR
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CS5BBCR_A: .long CS5BBCR
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CS6ABCR_A: .long CS6ABCR
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CS6BBCR_A: .long CS6BBCR
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CS0WCR_A: .long CS0WCR
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CS4WCR_A: .long CS4WCR
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CS5AWCR_A: .long CS5AWCR
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CS5BWCR_A: .long CS5BWCR
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CS6AWCR_A: .long CS6AWCR
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CS6BWCR_A: .long CS6BWCR
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CMNCR_D: .long 0x00000013
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CS0BCR_D: .long 0x24920400
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CS4BCR_D: .long 0x24920400
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CS5ABCR_D: .long 0x24920400
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CS5BBCR_D: .long 0x7fff0600
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CS6ABCR_D: .long 0x24920400
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CS6BBCR_D: .long 0x24920600
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CS0WCR_D: .long 0x00000480
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CS4WCR_D: .long 0x00000480
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CS5AWCR_D: .long 0x00000380
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CS5BWCR_D: .long 0x00000600
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CS6AWCR_D: .long 0x00000300
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CS6BWCR_D: .long 0x00000540
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CCR_A: .long 0xff00001c
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CCR_D: .long 0x0000090d
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SLEEP_CNT: .long 0x00000800
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SR_MASK_D: .long 0xEFFFFF0F
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