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c759a01a00
The memory map on the 8641hpcn is modified to look more like the 85xx boards; this is a step towards a more standardized layout going forward. As part of this change, we now relocate the flash. The regions for some of the mappings were far larger than they needed to be. I have reduced the mappings to match the actual sizes supported by the hardware. In addition I have removed the comments at the head of the BAT blocks in the config file, rather than updating them. These get horribly out of date, and it's a simple matter to look at the defines to see what they are set to since everything is right here in the same file. Documentation has been changed to reflect the new map, as this change is user visible, and affects the OS which runs post-uboot. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
163 lines
4.8 KiB
Plaintext
163 lines
4.8 KiB
Plaintext
Freescale MPC8641HPCN board
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===========================
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Created 05/24/2006 Haiying Wang
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-------------------------------
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1. Building U-Boot
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------------------
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The 86xx HPCN code base is known to compile using:
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Binutils 2.15, Gcc 3.4.3, Glibc 2.3.3
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$ make MPC8641HPCN_config
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Configuring for MPC8641HPCN board...
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$ make
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2. Switch and Jumper Setting
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----------------------------
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Jumpers:
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J14 Pins 1-2 (near plcc32 socket)
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Switches:
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SW1(1-5) = 01100 CONFIG_SYS_COREPLL = 01000 :: CORE = 2:1
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01100 :: CORE = 2.5:1
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10000 :: CORE = 3:1
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11100 :: CORE = 3.5:1
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10100 :: CORE = 4:1
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01110 :: CORE = 4.5:1
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SW1(6-8) = 001 CONFIG_SYS_SYSCLK = 000 :: SYSCLK = 33MHz
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001 :: SYSCLK = 40MHz
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SW2(1-4) = 1100 CONFIG_SYS_CCBPLL = 0010 :: 2X
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0100 :: 4X
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0110 :: 6X
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1000 :: 8X
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1010 :: 10X
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1100 :: 12X
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1110 :: 14X
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0000 :: 16X
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SW2(5-8) = 1110 CONFIG_SYS_BOOTLOC = 1110 :: boot 16-bit localbus
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SW3(1-7) = 0011000 CONFIG_SYS_VID = 0011000 :: VCORE = 1.2V
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0100000 :: VCORE = 1.11V
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SW3(8) = 0 VCC_PLAT = 0 :: VCC_PLAT = 1.2V
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1 :: VCC_PLAT = 1.0V
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SW4(1-2) = 11 CONFIG_SYS_HOSTMODE = 11 :: both prots host/root
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SW4(3-4) = 11 CONFIG_SYS_BOOTSEQ = 11 :: no boot seq
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SW4(5-8) = 0011 CONFIG_SYS_IOPORT = 0011 :: both PEX
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SW5(1) = 1 CONFIG_SYS_FLASHMAP = 1 :: boot from flash
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0 :: boot from PromJet
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SW5(2) = 1 CONFIG_SYS_FLASHBANK = 1 :: swap upper/lower
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halves (virtual banks)
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0 :: normal
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SW5(3) = 0 CONFIG_SYS_FLASHWP = 0 :: not protected
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SW5(4) = 0 CONFIG_SYS_PORTDIV = 1 :: 2:1 for PD4
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1:1 for PD6
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SW5(5-6) = 11 CONFIG_SYS_PIXISOPT = 11 :: s/w determined
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SW5(7-8) = 11 CONFIG_SYS_LADOPT = 11 :: s/w determined
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SW6(1) = 1 CONFIG_SYS_CPUBOOT = 1 :: no boot holdoff
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SW6(2) = 1 CONFIG_SYS_BOOTADDR = 1 :: no traslation
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SW6(3-5) = 000 CONFIG_SYS_REFCLKSEL = 000 :: 100MHZ
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SW6(6) = 1 CONFIG_SYS_SERROM_ADDR= 1 ::
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SW6(7) = 1 CONFIG_SYS_MEMDEBUG = 1 ::
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SW6(8) = 1 CONFIG_SYS_DDRDEBUG = 1 ::
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SW8(1) = 1 ACZ_SYNC = 1 :: 48MHz on TP49
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SW8(2) = 1 ACB_SYNC = 1 :: THRMTRIP disabled
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SW8(3) = 1 ACZ_SDOUT = 1 :: p4 mode
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SW8(4) = 1 ACB_SDOUT = 1 :: PATA freq. = 133MHz
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SW8(5) = 0 SUSLED = 0 :: SouthBridge Mode
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SW8(6) = 0 SPREAD = 0 :: REFCLK SSCG Disabled
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SW8(7) = 1 ACPWR = 1 :: non-battery
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SW8(8) = 0 CONFIG_SYS_IDWP = 0 :: write enable
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3. Flash U-Boot
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---------------
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The flash range 0xEF800000 to 0xEFFFFFFF can be divided into 2 halves.
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It is possible to use either half to boot using u-boot. Switch 5 bit 2
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is used for this purpose.
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0xEF800000 to 0xEFBFFFFF - 4MB
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0xEFC00000 to 0xEFFFFFFF - 4MB
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When this bit is 0, U-Boot is at 0xEFF00000.
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When this bit is 1, U-Boot is at 0xEFB00000.
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Use the above mentioned flash commands to program the other half, and
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use switch 5, bit 2 to alternate between the halves. Note: The booting
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version of U-Boot will always be at 0xEFF00000.
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To Flash U-Boot into the booting bank (0xEFC00000 - 0xEFFFFFFF):
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tftp 1000000 u-boot.bin
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protect off all
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erase eff00000 +$filesize
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cp.b 1000000 eff00000 $filesize
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or use tftpflash command:
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run tftpflash
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To Flash U-boot into the alternative bank (0xEF800000 - 0xEFBFFFFF):
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tftp 1000000 u-boot.bin
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erase efb00000 +$filesize
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cp.b 1000000 efb00000 $filesize
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4. Memory Map
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-------------
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NOTE: RIO and PCI are mutually exclusive, so they share an address
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Memory Range Device Size
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------------ ------ ----
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0x0000_0000 0x7fff_ffff DDR 2G
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0x8000_0000 0x9fff_ffff RIO MEM 512M
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0x8000_0000 0x9fff_ffff PCI1/PEX1 MEM 512M
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0xa000_0000 0xbfff_ffff PCI2/PEX2 MEM 512M
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0xffe0_0000 0xffef_ffff CCSR 1M
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0xffdf_0000 0xffdf_7fff PIXIS 8K
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0xffdf_8000 0xffdf_ffff CF 8K
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0xf840_0000 0xf840_3fff Stack space 32K
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0xffc0_0000 0xffc0_ffff PCI1/PEX1 IO 64K
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0xffc1_0000 0xffc1_ffff PCI2/PEX2 IO 64K
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0xef80_0000 0xefff_ffff Flash 8M
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5. pixis_reset command
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--------------------
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A new command, "pixis_reset", is introduced to reset mpc8641hpcn board
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using the FPGA sequencer. When the board restarts, it has the option
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of using either the current or alternate flash bank as the boot
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image, with or without the watchdog timer enabled, and finally with
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or without frequency changes.
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Usage is;
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pixis_reset
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pixis_reset altbank
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pixis_reset altbank wd
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pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
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pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
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Examples;
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/* reset to current bank, like "reset" command */
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pixis_reset
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/* reset board but use the to alternate flash bank */
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pixis_reset altbank
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/* reset board, use alternate flash bank with watchdog timer enabled*/
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pixis_reset altbank wd
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/* reset board to alternate bank with frequency changed.
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* 40 is SYSCLK, 2.5 is COREPLL ratio, 10 is MPXPLL ratio
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*/
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pixis-reset altbank cf 40 2.5 10
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Valid clock choices are in the 8641 Reference Manuals.
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