mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-29 22:33:44 +09:00
f56348af5d
The purpose of this patch is to prepare for adding the OMAP4 architecture, which is Cortex A9 Cortex A8 and A9 both belong to the armv7 architecture, hence the name change. The two architectures are similar enough that substantial code can be shared. Signed-off-by: Aneesh V <aneesh@ti.com> Signed-off-by: Steve Sakoman <steve@sakoman.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
115 lines
2.4 KiB
C
115 lines
2.4 KiB
C
/*
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* (C) Copyright 2007
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* Sascha Hauer, Pengutronix
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*
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* (C) Copyright 2009 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/clock.h>
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#include <asm/errno.h>
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#include <asm/io.h>
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#ifdef CONFIG_FSL_ESDHC
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#include <fsl_esdhc.h>
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#endif
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u32 get_cpu_rev(void)
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{
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int reg;
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int system_rev;
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reg = __raw_readl(ROM_SI_REV);
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switch (reg) {
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case 0x02:
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system_rev = 0x51000 | CHIP_REV_1_1;
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break;
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case 0x10:
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if ((__raw_readl(GPIO1_BASE_ADDR + 0x0) & (0x1 << 22)) == 0)
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system_rev = 0x51000 | CHIP_REV_2_5;
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else
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system_rev = 0x51000 | CHIP_REV_2_0;
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break;
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case 0x20:
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system_rev = 0x51000 | CHIP_REV_3_0;
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break;
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return system_rev;
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default:
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system_rev = 0x51000 | CHIP_REV_1_0;
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break;
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}
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return system_rev;
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}
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#if defined(CONFIG_DISPLAY_CPUINFO)
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int print_cpuinfo(void)
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{
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u32 cpurev;
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cpurev = get_cpu_rev();
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printf("CPU: Freescale i.MX51 family rev%d.%d at %d MHz\n",
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(cpurev & 0xF0) >> 4,
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(cpurev & 0x0F) >> 4,
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mxc_get_clock(MXC_ARM_CLK) / 1000000);
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return 0;
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}
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#endif
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/*
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* Initializes on-chip ethernet controllers.
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* to override, implement board_eth_init()
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*/
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#if defined(CONFIG_FEC_MXC)
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extern int fecmxc_initialize(bd_t *bis);
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#endif
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int cpu_eth_init(bd_t *bis)
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{
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int rc = -ENODEV;
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#if defined(CONFIG_FEC_MXC)
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rc = fecmxc_initialize(bis);
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#endif
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return rc;
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}
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/*
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* Initializes on-chip MMC controllers.
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* to override, implement board_mmc_init()
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*/
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int cpu_mmc_init(bd_t *bis)
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{
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#ifdef CONFIG_FSL_ESDHC
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return fsl_esdhc_mmc_init(bis);
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#else
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return 0;
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#endif
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}
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void reset_cpu(ulong addr)
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{
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__raw_writew(4, WDOG1_BASE_ADDR);
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}
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