mirror of
https://github.com/brain-hackers/u-boot-brain
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f56348af5d
The purpose of this patch is to prepare for adding the OMAP4 architecture, which is Cortex A9 Cortex A8 and A9 both belong to the armv7 architecture, hence the name change. The two architectures are similar enough that substantial code can be shared. Signed-off-by: Aneesh V <aneesh@ti.com> Signed-off-by: Steve Sakoman <steve@sakoman.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
292 lines
6.6 KiB
ArmAsm
292 lines
6.6 KiB
ArmAsm
/*
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* Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
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*
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* (C) Copyright 2009 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/asm-offsets.h>
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/*
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* L2CC Cache setup/invalidation/disable
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*/
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.macro init_l2cc
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/* explicitly disable L2 cache */
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mrc 15, 0, r0, c1, c0, 1
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bic r0, r0, #0x2
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mcr 15, 0, r0, c1, c0, 1
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/* reconfigure L2 cache aux control reg */
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mov r0, #0xC0 /* tag RAM */
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add r0, r0, #0x4 /* data RAM */
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orr r0, r0, #(1 << 24) /* disable write allocate delay */
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orr r0, r0, #(1 << 23) /* disable write allocate combine */
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orr r0, r0, #(1 << 22) /* disable write allocate */
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cmp r3, #0x10 /* r3 contains the silicon rev */
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/* disable write combine for TO 2 and lower revs */
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orrls r0, r0, #(1 << 25)
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mcr 15, 1, r0, c9, c0, 2
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.endm /* init_l2cc */
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/* AIPS setup - Only setup MPROTx registers.
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* The PACR default values are good.*/
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.macro init_aips
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/*
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* Set all MPROTx to be non-bufferable, trusted for R/W,
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* not forced to user-mode.
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*/
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ldr r0, =AIPS1_BASE_ADDR
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ldr r1, =0x77777777
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str r1, [r0, #0x0]
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str r1, [r0, #0x4]
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ldr r0, =AIPS2_BASE_ADDR
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str r1, [r0, #0x0]
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str r1, [r0, #0x4]
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/*
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* Clear the on and off peripheral modules Supervisor Protect bit
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* for SDMA to access them. Did not change the AIPS control registers
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* (offset 0x20) access type
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*/
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.endm /* init_aips */
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/* M4IF setup */
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.macro init_m4if
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/* VPU and IPU given higher priority (0x4)
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* IPU accesses with ID=0x1 given highest priority (=0xA)
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*/
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ldr r0, =M4IF_BASE_ADDR
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ldr r1, =0x00000203
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str r1, [r0, #0x40]
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ldr r1, =0x0
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str r1, [r0, #0x44]
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ldr r1, =0x00120125
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str r1, [r0, #0x9C]
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ldr r1, =0x001901A3
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str r1, [r0, #0x48]
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.endm /* init_m4if */
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.macro setup_pll pll, freq
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ldr r2, =\pll
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ldr r1, =0x00001232
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str r1, [r2, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
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mov r1, #0x2
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str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
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str r3, [r2, #PLL_DP_OP]
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str r3, [r2, #PLL_DP_HFS_OP]
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str r4, [r2, #PLL_DP_MFD]
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str r4, [r2, #PLL_DP_HFS_MFD]
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str r5, [r2, #PLL_DP_MFN]
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str r5, [r2, #PLL_DP_HFS_MFN]
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ldr r1, =0x00001232
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str r1, [r2, #PLL_DP_CTL]
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1: ldr r1, [r2, #PLL_DP_CTL]
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ands r1, r1, #0x1
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beq 1b
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.endm
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.macro init_clock
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ldr r0, =CCM_BASE_ADDR
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/* Gate of clocks to the peripherals first */
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ldr r1, =0x3FFFFFFF
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str r1, [r0, #CLKCTL_CCGR0]
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ldr r1, =0x0
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str r1, [r0, #CLKCTL_CCGR1]
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str r1, [r0, #CLKCTL_CCGR2]
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str r1, [r0, #CLKCTL_CCGR3]
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ldr r1, =0x00030000
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str r1, [r0, #CLKCTL_CCGR4]
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ldr r1, =0x00FFF030
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str r1, [r0, #CLKCTL_CCGR5]
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ldr r1, =0x00000300
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str r1, [r0, #CLKCTL_CCGR6]
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/* Disable IPU and HSC dividers */
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mov r1, #0x60000
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str r1, [r0, #CLKCTL_CCDR]
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/* Make sure to switch the DDR away from PLL 1 */
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ldr r1, =0x19239145
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str r1, [r0, #CLKCTL_CBCDR]
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/* make sure divider effective */
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1: ldr r1, [r0, #CLKCTL_CDHIPR]
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cmp r1, #0x0
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bne 1b
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/* Switch ARM to step clock */
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mov r1, #0x4
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str r1, [r0, #CLKCTL_CCSR]
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mov r3, #DP_OP_800
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mov r4, #DP_MFD_800
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mov r5, #DP_MFN_800
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setup_pll PLL1_BASE_ADDR
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mov r3, #DP_OP_665
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mov r4, #DP_MFD_665
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mov r5, #DP_MFN_665
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setup_pll PLL3_BASE_ADDR
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/* Switch peripheral to PLL 3 */
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ldr r0, =CCM_BASE_ADDR
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ldr r1, =0x000010C0
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orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
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str r1, [r0, #CLKCTL_CBCMR]
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ldr r1, =0x13239145
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str r1, [r0, #CLKCTL_CBCDR]
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mov r3, #DP_OP_665
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mov r4, #DP_MFD_665
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mov r5, #DP_MFN_665
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setup_pll PLL2_BASE_ADDR
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/* Switch peripheral to PLL2 */
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ldr r0, =CCM_BASE_ADDR
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ldr r1, =0x19239145
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str r1, [r0, #CLKCTL_CBCDR]
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ldr r1, =0x000020C0
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orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
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str r1, [r0, #CLKCTL_CBCMR]
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mov r3, #DP_OP_216
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mov r4, #DP_MFD_216
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mov r5, #DP_MFN_216
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setup_pll PLL3_BASE_ADDR
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/* Set the platform clock dividers */
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ldr r0, =ARM_BASE_ADDR
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ldr r1, =0x00000725
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str r1, [r0, #0x14]
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ldr r0, =CCM_BASE_ADDR
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/* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */
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ldr r1, =0x0
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ldr r3, [r1, #ROM_SI_REV]
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cmp r3, #0x10
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movls r1, #0x1
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movhi r1, #0
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str r1, [r0, #CLKCTL_CACRR]
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/* Switch ARM back to PLL 1 */
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mov r1, #0
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str r1, [r0, #CLKCTL_CCSR]
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/* setup the rest */
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/* Use lp_apm (24MHz) source for perclk */
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ldr r1, =0x000020C2
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orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
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str r1, [r0, #CLKCTL_CBCMR]
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/* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
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ldr r1, =CONFIG_SYS_CLKTL_CBCDR
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str r1, [r0, #CLKCTL_CBCDR]
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/* Restore the default values in the Gate registers */
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ldr r1, =0xFFFFFFFF
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str r1, [r0, #CLKCTL_CCGR0]
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str r1, [r0, #CLKCTL_CCGR1]
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str r1, [r0, #CLKCTL_CCGR2]
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str r1, [r0, #CLKCTL_CCGR3]
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str r1, [r0, #CLKCTL_CCGR4]
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str r1, [r0, #CLKCTL_CCGR5]
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str r1, [r0, #CLKCTL_CCGR6]
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/* Use PLL 2 for UART's, get 66.5MHz from it */
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ldr r1, =0xA5A2A020
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str r1, [r0, #CLKCTL_CSCMR1]
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ldr r1, =0x00C30321
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str r1, [r0, #CLKCTL_CSCDR1]
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/* make sure divider effective */
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1: ldr r1, [r0, #CLKCTL_CDHIPR]
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cmp r1, #0x0
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bne 1b
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mov r1, #0x0
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str r1, [r0, #CLKCTL_CCDR]
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/* for cko - for ARM div by 8 */
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mov r1, #0x000A0000
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add r1, r1, #0x00000F0
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str r1, [r0, #CLKCTL_CCOSR]
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.endm
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.macro setup_wdog
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ldr r0, =WDOG1_BASE_ADDR
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mov r1, #0x30
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strh r1, [r0]
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.endm
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.section ".text.init", "x"
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.globl lowlevel_init
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lowlevel_init:
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ldr r0, =GPIO1_BASE_ADDR
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ldr r1, [r0, #0x0]
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orr r1, r1, #(1 << 23)
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str r1, [r0, #0x0]
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ldr r1, [r0, #0x4]
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orr r1, r1, #(1 << 23)
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str r1, [r0, #0x4]
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#ifdef ENABLE_IMPRECISE_ABORT
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mrs r1, spsr /* save old spsr */
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mrs r0, cpsr /* read out the cpsr */
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bic r0, r0, #0x100 /* clear the A bit */
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msr spsr, r0 /* update spsr */
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add lr, pc, #0x8 /* update lr */
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movs pc, lr /* update cpsr */
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nop
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nop
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nop
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nop
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msr spsr, r1 /* restore old spsr */
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#endif
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init_l2cc
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init_aips
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init_m4if
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init_clock
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/* r12 saved upper lr*/
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mov pc,lr
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/* Board level setting value */
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DDR_PERCHARGE_CMD: .word 0x04008008
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DDR_REFRESH_CMD: .word 0x00008010
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DDR_LMR1_W: .word 0x00338018
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DDR_LMR_CMD: .word 0xB2220000
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DDR_TIMING_W: .word 0xB02567A9
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DDR_MISC_W: .word 0x000A0104
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