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https://github.com/brain-hackers/u-boot-brain
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6875149740
P2020 integrated 3 PCIe controllers, which is compatible with the PCI Express™ Base Specification, Revision 1.0a, and this patch is to add DT node for each PCIe controller. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
41 lines
1.0 KiB
Plaintext
41 lines
1.0 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* P2020RDB-PC Device Tree Source
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*
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* Copyright 2013 - 2015 Freescale Semiconductor Inc.
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* Copyright 2019 NXP
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*/
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/include/ "p2020.dtsi"
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/ {
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model = "fsl,P2020RDB-PC";
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compatible = "fsl,P2020RDB-PC";
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&mpic>;
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soc: soc@ffe00000 {
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ranges = <0x0 0x0 0xffe00000 0x100000>;
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};
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pci2: pcie@ffe08000 {
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reg = <0x0 0xffe08000 0x0 0x1000>; /* registers */
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status = "disabled";
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};
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pci1: pcie@ffe09000 {
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reg = <0x0 0xffe09000 0x0 0x1000>; /* registers */
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ranges = <0x01000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x00010000 /* downstream I/O */
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0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */
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};
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pci0: pcie@ffe0a000 {
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reg = <0x0 0xffe0a000 0x0 0x1000>; /* registers */
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ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000 /* downstream I/O */
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0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */
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};
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};
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/include/ "p2020-post.dtsi"
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