mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
167 lines
3.4 KiB
ArmAsm
167 lines
3.4 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2013 Philippe Reynes <tremyfr@yahoo.fr>
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*/
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#include <config.h>
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#include <generated/asm-offsets.h>
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#include <asm/macro.h>
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#include <asm/arch/imx-regs.h>
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#include "apf27.h"
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.macro init_aipi
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/*
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* setup AIPI1 and AIPI2
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*/
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write32 AIPI1_PSR0, ACFG_AIPI1_PSR0_VAL
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write32 AIPI1_PSR1, ACFG_AIPI1_PSR1_VAL
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write32 AIPI2_PSR0, ACFG_AIPI2_PSR0_VAL
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write32 AIPI2_PSR1, ACFG_AIPI2_PSR1_VAL
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/* Change SDRAM signal strengh */
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ldr r0, =GPCR
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ldr r1, =ACFG_GPCR_VAL
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ldr r5, [r0]
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orr r5, r5, r1
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str r5, [r0]
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.endm /* init_aipi */
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.macro init_clock
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ldr r0, =CSCR
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/* disable MPLL/SPLL first */
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ldr r1, [r0]
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bic r1, r1, #(CSCR_MPEN|CSCR_SPEN)
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str r1, [r0]
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/*
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* pll clock initialization predefined in apf27.h
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*/
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write32 MPCTL0, ACFG_MPCTL0_VAL
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write32 SPCTL0, ACFG_SPCTL0_VAL
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write32 CSCR, ACFG_CSCR_VAL|CSCR_MPLL_RESTART|CSCR_SPLL_RESTART
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/*
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* add some delay here
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*/
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mov r1, #0x1000
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1: subs r1, r1, #0x1
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bne 1b
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/* peripheral clock divider */
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write32 PCDR0, ACFG_PCDR0_VAL
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write32 PCDR1, ACFG_PCDR1_VAL
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/* Configure PCCR0 and PCCR1 */
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write32 PCCR0, ACFG_PCCR0_VAL
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write32 PCCR1, ACFG_PCCR1_VAL
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.endm /* init_clock */
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.macro init_ddr
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/* wait for SDRAM/LPDDR ready (SDRAMRDY) */
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ldr r0, =IMX_ESD_BASE
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ldr r4, =ESDMISC_SDRAM_RDY
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2: ldr r1, [r0, #ESDMISC_ROF]
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ands r1, r1, r4
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bpl 2b
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/* LPDDR Soft Reset Mobile/Low Power DDR SDRAM. */
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ldr r0, =IMX_ESD_BASE
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ldr r4, =ACFG_ESDMISC_VAL
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orr r1, r4, #ESDMISC_MDDR_DL_RST
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str r1, [r0, #ESDMISC_ROF]
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/* Hold for more than 200ns */
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ldr r1, =0x10000
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1: subs r1, r1, #0x1
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bne 1b
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str r4, [r0]
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ldr r0, =IMX_ESD_BASE
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ldr r1, =ACFG_SDRAM_ESDCFG_REGISTER_VAL
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str r1, [r0, #ESDCFG0_ROF]
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ldr r0, =IMX_ESD_BASE
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ldr r1, =ACFG_PRECHARGE_CMD
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str r1, [r0, #ESDCTL0_ROF]
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/* write8(0xA0001000, any value) */
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ldr r1, =PHYS_SDRAM_1+ACFG_SDRAM_PRECHARGE_ALL_VAL
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strb r2, [r1]
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ldr r1, =ACFG_AUTOREFRESH_CMD
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str r1, [r0, #ESDCTL0_ROF]
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ldr r4, =PHYS_SDRAM_1 /* CSD0 base address */
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ldr r6,=0x7 /* load loop counter */
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1: str r5,[r4] /* run auto-refresh cycle to array 0 */
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subs r6,r6,#1
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bne 1b
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ldr r1, =ACFG_SET_MODE_REG_CMD
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str r1, [r0, #ESDCTL0_ROF]
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/* set standard mode register */
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ldr r4, = PHYS_SDRAM_1+ACFG_SDRAM_MODE_REGISTER_VAL
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strb r2, [r4]
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/* set extended mode register */
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ldr r4, =PHYS_SDRAM_1+ACFG_SDRAM_EXT_MODE_REGISTER_VAL
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strb r5, [r4]
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ldr r1, =ACFG_NORMAL_RW_CMD
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str r1, [r0, #ESDCTL0_ROF]
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/* 2nd sdram */
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ldr r0, =IMX_ESD_BASE
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ldr r1, =ACFG_SDRAM_ESDCFG_REGISTER_VAL
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str r1, [r0, #ESDCFG1_ROF]
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ldr r0, =IMX_ESD_BASE
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ldr r1, =ACFG_PRECHARGE_CMD
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str r1, [r0, #ESDCTL1_ROF]
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/* write8(0xB0001000, any value) */
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ldr r1, =PHYS_SDRAM_2+ACFG_SDRAM_PRECHARGE_ALL_VAL
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strb r2, [r1]
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ldr r1, =ACFG_AUTOREFRESH_CMD
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str r1, [r0, #ESDCTL1_ROF]
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ldr r4, =PHYS_SDRAM_2 /* CSD1 base address */
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ldr r6,=0x7 /* load loop counter */
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1: str r5,[r4] /* run auto-refresh cycle to array 0 */
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subs r6,r6,#1
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bne 1b
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ldr r1, =ACFG_SET_MODE_REG_CMD
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str r1, [r0, #ESDCTL1_ROF]
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/* set standard mode register */
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ldr r4, =PHYS_SDRAM_2+ACFG_SDRAM_MODE_REGISTER_VAL
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strb r2, [r4]
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/* set extended mode register */
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ldr r4, =PHYS_SDRAM_2+ACFG_SDRAM_EXT_MODE_REGISTER_VAL
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strb r2, [r4]
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ldr r1, =ACFG_NORMAL_RW_CMD
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str r1, [r0, #ESDCTL1_ROF]
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.endm /* init_ddr */
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.globl lowlevel_init
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lowlevel_init:
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init_aipi
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init_clock
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#ifdef CONFIG_SPL_BUILD
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init_ddr
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#endif
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mov pc, lr
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