mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
150 lines
5.5 KiB
C
150 lines
5.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2015, Freescale Semiconductor, Inc.
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*/
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#ifndef __ARCH_ARM_MACH_S32V234_SIUL_H__
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#define __ARCH_ARM_MACH_S32V234_SIUL_H__
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#include "ddr.h"
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#define SIUL2_MIDR1 (SIUL2_BASE_ADDR + 0x00000004)
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#define SIUL2_MIDR2 (SIUL2_BASE_ADDR + 0x00000008)
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#define SIUL2_DISR0 (SIUL2_BASE_ADDR + 0x00000010)
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#define SIUL2_DIRER0 (SIUL2_BASE_ADDR + 0x00000018)
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#define SIUL2_DIRSR0 (SIUL2_BASE_ADDR + 0x00000020)
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#define SIUL2_IREER0 (SIUL2_BASE_ADDR + 0x00000028)
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#define SIUL2_IFEER0 (SIUL2_BASE_ADDR + 0x00000030)
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#define SIUL2_IFER0 (SIUL2_BASE_ADDR + 0x00000038)
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#define SIUL2_IFMCR_BASE (SIUL2_BASE_ADDR + 0x00000040)
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#define SIUL2_IFMCRn(i) (SIUL2_IFMCR_BASE + 4 * (i))
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#define SIUL2_IFCPR (SIUL2_BASE_ADDR + 0x000000C0)
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/* SIUL2_MSCR specifications as stated in Reference Manual:
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* 0 - 359 Output Multiplexed Signal Configuration Registers
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* 512- 1023 Input Multiplexed Signal Configuration Registers */
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#define SIUL2_MSCR_BASE (SIUL2_BASE_ADDR + 0x00000240)
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#define SIUL2_MSCRn(i) (SIUL2_MSCR_BASE + 4 * (i))
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#define SIUL2_IMCR_BASE (SIUL2_BASE_ADDR + 0x00000A40)
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#define SIUL2_IMCRn(i) (SIUL2_IMCR_BASE + 4 * (i))
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#define SIUL2_GPDO_BASE (SIUL2_BASE_ADDR + 0x00001300)
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#define SIUL2_GPDOn(i) (SIUL2_GPDO_BASE + 4 * (i))
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#define SIUL2_GPDI_BASE (SIUL2_BASE_ADDR + 0x00001500)
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#define SIUL2_GPDIn(i) (SIUL2_GPDI_BASE + 4 * (i))
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#define SIUL2_PGPDO_BASE (SIUL2_BASE_ADDR + 0x00001700)
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#define SIUL2_PGPDOn(i) (SIUL2_PGPDO_BASE + 2 * (i))
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#define SIUL2_PGPDI_BASE (SIUL2_BASE_ADDR + 0x00001740)
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#define SIUL2_PGPDIn(i) (SIUL2_PGPDI_BASE + 2 * (i))
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#define SIUL2_MPGPDO_BASE (SIUL2_BASE_ADDR + 0x00001780)
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#define SIUL2_MPGPDOn(i) (SIUL2_MPGPDO_BASE + 4 * (i))
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/* SIUL2_MSCR masks */
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#define SIUL2_MSCR_DDR_DO_TRIM(v) ((v) & 0xC0000000)
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#define SIUL2_MSCR_DDR_DO_TRIM_MIN (0 << 30)
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#define SIUL2_MSCR_DDR_DO_TRIM_50PS (1 << 30)
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#define SIUL2_MSCR_DDR_DO_TRIM_100PS (2 << 30)
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#define SIUL2_MSCR_DDR_DO_TRIM_150PS (3 << 30)
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#define SIUL2_MSCR_DDR_INPUT(v) ((v) & 0x20000000)
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#define SIUL2_MSCR_DDR_INPUT_CMOS (0 << 29)
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#define SIUL2_MSCR_DDR_INPUT_DIFF_DDR (1 << 29)
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#define SIUL2_MSCR_DDR_SEL(v) ((v) & 0x18000000)
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#define SIUL2_MSCR_DDR_SEL_DDR3 (0 << 27)
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#define SIUL2_MSCR_DDR_SEL_LPDDR2 (2 << 27)
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#define SIUL2_MSCR_DDR_ODT(v) ((v) & 0x07000000)
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#define SIUL2_MSCR_DDR_ODT_120ohm (1 << 24)
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#define SIUL2_MSCR_DDR_ODT_60ohm (2 << 24)
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#define SIUL2_MSCR_DDR_ODT_40ohm (3 << 24)
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#define SIUL2_MSCR_DDR_ODT_30ohm (4 << 24)
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#define SIUL2_MSCR_DDR_ODT_24ohm (5 << 24)
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#define SIUL2_MSCR_DDR_ODT_20ohm (6 << 24)
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#define SIUL2_MSCR_DDR_ODT_17ohm (7 << 24)
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#define SIUL2_MSCR_DCYCLE_TRIM(v) ((v) & 0x00C00000)
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#define SIUL2_MSCR_DCYCLE_TRIM_NONE (0 << 22)
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#define SIUL2_MSCR_DCYCLE_TRIM_LEFT (1 << 22)
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#define SIUL2_MSCR_DCYCLE_TRIM_RIGHT (2 << 22)
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#define SIUL2_MSCR_OBE(v) ((v) & 0x00200000)
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#define SIUL2_MSCR_OBE_EN (1 << 21)
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#define SIUL2_MSCR_ODE(v) ((v) & 0x00100000)
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#define SIUL2_MSCR_ODE_EN (1 << 20)
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#define SIUL2_MSCR_IBE(v) ((v) & 0x00010000)
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#define SIUL2_MSCR_IBE_EN (1 << 19)
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#define SIUL2_MSCR_HYS(v) ((v) & 0x00400000)
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#define SIUL2_MSCR_HYS_EN (1 << 18)
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#define SIUL2_MSCR_INV(v) ((v) & 0x00020000)
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#define SIUL2_MSCR_INV_EN (1 << 17)
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#define SIUL2_MSCR_PKE(v) ((v) & 0x00010000)
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#define SIUL2_MSCR_PKE_EN (1 << 16)
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#define SIUL2_MSCR_SRE(v) ((v) & 0x0000C000)
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#define SIUL2_MSCR_SRE_SPEED_LOW_50 (0 << 14)
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#define SIUL2_MSCR_SRE_SPEED_LOW_100 (1 << 14)
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#define SIUL2_MSCR_SRE_SPEED_HIGH_100 (2 << 14)
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#define SIUL2_MSCR_SRE_SPEED_HIGH_200 (3 << 14)
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#define SIUL2_MSCR_PUE(v) ((v) & 0x00002000)
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#define SIUL2_MSCR_PUE_EN (1 << 13)
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#define SIUL2_MSCR_PUS(v) ((v) & 0x00001800)
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#define SIUL2_MSCR_PUS_100K_DOWN (0 << 11)
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#define SIUL2_MSCR_PUS_50K_DOWN (1 << 11)
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#define SIUL2_MSCR_PUS_100K_UP (2 << 11)
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#define SIUL2_MSCR_PUS_33K_UP (3 << 11)
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#define SIUL2_MSCR_DSE(v) ((v) & 0x00000700)
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#define SIUL2_MSCR_DSE_240ohm (1 << 8)
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#define SIUL2_MSCR_DSE_120ohm (2 << 8)
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#define SIUL2_MSCR_DSE_80ohm (3 << 8)
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#define SIUL2_MSCR_DSE_60ohm (4 << 8)
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#define SIUL2_MSCR_DSE_48ohm (5 << 8)
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#define SIUL2_MSCR_DSE_40ohm (6 << 8)
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#define SIUL2_MSCR_DSE_34ohm (7 << 8)
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#define SIUL2_MSCR_CRPOINT_TRIM(v) ((v) & 0x000000C0)
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#define SIUL2_MSCR_CRPOINT_TRIM_1 (1 << 6)
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#define SIUL2_MSCR_SMC(v) ((v) & 0x00000020)
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#define SIUL2_MSCR_MUX_MODE(v) ((v) & 0x0000000f)
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#define SIUL2_MSCR_MUX_MODE_ALT1 (0x1)
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#define SIUL2_MSCR_MUX_MODE_ALT2 (0x2)
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#define SIUL2_MSCR_MUX_MODE_ALT3 (0x3)
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/* UART settings */
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#define SIUL2_UART0_TXD_PAD 12
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#define SIUL2_UART_TXD (SIUL2_MSCR_OBE_EN | SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_DSE_60ohm | \
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SIUL2_MSCR_SRE_SPEED_LOW_100 | SIUL2_MSCR_MUX_MODE_ALT1)
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#define SIUL2_UART0_MSCR_RXD_PAD 11
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#define SIUL2_UART0_IMCR_RXD_PAD 200
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#define SIUL2_UART_MSCR_RXD (SIUL2_MSCR_PUE_EN | SIUL2_MSCR_IBE_EN | SIUL2_MSCR_DCYCLE_TRIM_RIGHT)
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#define SIUL2_UART_IMCR_RXD (SIUL2_MSCR_MUX_MODE_ALT2)
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/* uSDHC settings */
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#define SIUL2_USDHC_PAD_CTRL_BASE (SIUL2_MSCR_SRE_SPEED_HIGH_200 | SIUL2_MSCR_OBE_EN | \
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SIUL2_MSCR_DSE_34ohm | SIUL2_MSCR_PKE_EN | SIUL2_MSCR_IBE_EN | \
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SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_PUE_EN )
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#define SIUL2_USDHC_PAD_CTRL_CMD (SIUL2_USDHC_PAD_CTRL_BASE | SIUL2_MSCR_MUX_MODE_ALT1)
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#define SIUL2_USDHC_PAD_CTRL_CLK (SIUL2_USDHC_PAD_CTRL_BASE | SIUL2_MSCR_MUX_MODE_ALT2)
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#define SIUL2_USDHC_PAD_CTRL_DAT0_3 (SIUL2_USDHC_PAD_CTRL_BASE | SIUL2_MSCR_MUX_MODE_ALT2)
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#define SIUL2_USDHC_PAD_CTRL_DAT4_7 (SIUL2_USDHC_PAD_CTRL_BASE | SIUL2_MSCR_MUX_MODE_ALT3)
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#endif /*__ARCH_ARM_MACH_S32V234_SIUL_H__ */
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