mirror of
https://github.com/brain-hackers/u-boot-brain
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41575d8e4c
This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
99 lines
2.3 KiB
C
99 lines
2.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Sandbox PMC for testing
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*
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* Copyright 2019 Google LLC
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*/
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#define LOG_CATEGORY UCLASS_ACPI_PMC
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#include <common.h>
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#include <dm.h>
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#include <log.h>
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#include <asm/io.h>
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#include <power/acpi_pmc.h>
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#define GPIO_GPE_CFG 0x1050
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/* Memory mapped IO registers behind PMC_BASE_ADDRESS */
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#define PRSTS 0x1000
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#define GEN_PMCON1 0x1020
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#define GEN_PMCON2 0x1024
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#define GEN_PMCON3 0x1028
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/* Offset of TCO registers from ACPI base I/O address */
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#define TCO_REG_OFFSET 0x60
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#define TCO1_STS 0x64
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#define TCO2_STS 0x66
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#define TCO1_CNT 0x68
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#define TCO2_CNT 0x6a
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struct sandbox_pmc_priv {
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ulong base;
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};
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static int sandbox_pmc_fill_power_state(struct udevice *dev)
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{
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struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
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upriv->tco1_sts = inw(upriv->acpi_base + TCO1_STS);
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upriv->tco2_sts = inw(upriv->acpi_base + TCO2_STS);
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upriv->prsts = readl(upriv->pmc_bar0 + PRSTS);
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upriv->gen_pmcon1 = readl(upriv->pmc_bar0 + GEN_PMCON1);
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upriv->gen_pmcon2 = readl(upriv->pmc_bar0 + GEN_PMCON2);
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upriv->gen_pmcon3 = readl(upriv->pmc_bar0 + GEN_PMCON3);
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return 0;
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}
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static int sandbox_prev_sleep_state(struct udevice *dev, int prev_sleep_state)
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{
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return prev_sleep_state;
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}
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static int sandbox_disable_tco(struct udevice *dev)
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{
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struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
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pmc_disable_tco_base(upriv->acpi_base + TCO_REG_OFFSET);
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return 0;
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}
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static int sandbox_pmc_probe(struct udevice *dev)
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{
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struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
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struct udevice *bus;
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ulong base;
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uclass_first_device(UCLASS_PCI, &bus);
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base = dm_pci_read_bar32(dev, 0);
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if (base == FDT_ADDR_T_NONE)
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return log_msg_ret("No base address", -EINVAL);
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upriv->pmc_bar0 = map_sysmem(base, 0x2000);
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upriv->gpe_cfg = (u32 *)(upriv->pmc_bar0 + GPIO_GPE_CFG);
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return pmc_ofdata_to_uc_platdata(dev);
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}
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static struct acpi_pmc_ops sandbox_pmc_ops = {
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.init = sandbox_pmc_fill_power_state,
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.prev_sleep_state = sandbox_prev_sleep_state,
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.disable_tco = sandbox_disable_tco,
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};
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static const struct udevice_id sandbox_pmc_ids[] = {
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{ .compatible = "sandbox,pmc" },
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{ }
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};
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U_BOOT_DRIVER(pmc_sandbox) = {
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.name = "pmc_sandbox",
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.id = UCLASS_ACPI_PMC,
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.of_match = sandbox_pmc_ids,
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.probe = sandbox_pmc_probe,
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.ops = &sandbox_pmc_ops,
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.priv_auto = sizeof(struct sandbox_pmc_priv),
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};
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