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https://github.com/brain-hackers/u-boot-brain
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c616a0df29
Add workaround for Cortex-A15 ARM erratum 798870 which says "If back-to-back speculative cache line fills (fill A and fill B) are issued from the L1 data cache of a CPU to the L2 cache, the second request (fill B) is then cancelled, and the second request would have detected a hazard against a recent write or eviction (write B) to the same cache line as fill B then the L2 logic might deadlock." Implementations for SoC families such as Exynos, OMAP5/DRA7 etc will be widely different. Every SoC has slightly different manner of setting up access to L2ACLR and similar registers since the Secure Monitor handling of Secure Monitor Call(smc) is diverse. Hence an weak function is introduced which may be overriden to implement SoC specific accessor implementation. Based on ARM errata Document revision 18.0 (22 Nov 2013) Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Matt Porter <mporter@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
146 lines
4.0 KiB
C
146 lines
4.0 KiB
C
/*
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* (C) Copyright 2010
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* Texas Instruments, <www.ti.com>
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* Aneesh V <aneesh@ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef ARMV7_H
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#define ARMV7_H
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/* Cortex-A9 revisions */
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#define MIDR_CORTEX_A9_R0P1 0x410FC091
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#define MIDR_CORTEX_A9_R1P2 0x411FC092
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#define MIDR_CORTEX_A9_R1P3 0x411FC093
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#define MIDR_CORTEX_A9_R2P10 0x412FC09A
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/* Cortex-A15 revisions */
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#define MIDR_CORTEX_A15_R0P0 0x410FC0F0
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#define MIDR_CORTEX_A15_R2P2 0x412FC0F2
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/* Cortex-A7 revisions */
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#define MIDR_CORTEX_A7_R0P0 0x410FC070
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#define MIDR_PRIMARY_PART_MASK 0xFF0FFFF0
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/* ID_PFR1 feature fields */
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#define CPUID_ARM_SEC_SHIFT 4
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#define CPUID_ARM_SEC_MASK (0xF << CPUID_ARM_SEC_SHIFT)
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#define CPUID_ARM_VIRT_SHIFT 12
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#define CPUID_ARM_VIRT_MASK (0xF << CPUID_ARM_VIRT_SHIFT)
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#define CPUID_ARM_GENTIMER_SHIFT 16
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#define CPUID_ARM_GENTIMER_MASK (0xF << CPUID_ARM_GENTIMER_SHIFT)
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/* valid bits in CBAR register / PERIPHBASE value */
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#define CBAR_MASK 0xFFFF8000
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/* CCSIDR */
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#define CCSIDR_LINE_SIZE_OFFSET 0
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#define CCSIDR_LINE_SIZE_MASK 0x7
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#define CCSIDR_ASSOCIATIVITY_OFFSET 3
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#define CCSIDR_ASSOCIATIVITY_MASK (0x3FF << 3)
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#define CCSIDR_NUM_SETS_OFFSET 13
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#define CCSIDR_NUM_SETS_MASK (0x7FFF << 13)
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/*
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* Values for InD field in CSSELR
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* Selects the type of cache
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*/
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#define ARMV7_CSSELR_IND_DATA_UNIFIED 0
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#define ARMV7_CSSELR_IND_INSTRUCTION 1
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/* Values for Ctype fields in CLIDR */
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#define ARMV7_CLIDR_CTYPE_NO_CACHE 0
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#define ARMV7_CLIDR_CTYPE_INSTRUCTION_ONLY 1
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#define ARMV7_CLIDR_CTYPE_DATA_ONLY 2
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#define ARMV7_CLIDR_CTYPE_INSTRUCTION_DATA 3
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#define ARMV7_CLIDR_CTYPE_UNIFIED 4
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#ifndef __ASSEMBLY__
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#include <linux/types.h>
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#include <asm/io.h>
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/*
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* CP15 Barrier instructions
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* Please note that we have separate barrier instructions in ARMv7
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* However, we use the CP15 based instructtions because we use
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* -march=armv5 in U-Boot
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*/
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#define CP15ISB asm volatile ("mcr p15, 0, %0, c7, c5, 4" : : "r" (0))
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#define CP15DSB asm volatile ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0))
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#define CP15DMB asm volatile ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0))
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/*
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* Workaround for ARM errata # 798870
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* Set L2ACTLR[7] to reissue any memory transaction in the L2 that has been
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* stalled for 1024 cycles to verify that its hazard condition still exists.
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*/
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static inline void v7_enable_l2_hazard_detect(void)
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{
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uint32_t val;
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/* L2ACTLR[7]: Enable hazard detect timeout */
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asm volatile ("mrc p15, 1, %0, c15, c0, 0\n\t" : "=r"(val));
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val |= (1 << 7);
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asm volatile ("mcr p15, 1, %0, c15, c0, 0\n\t" : : "r"(val));
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}
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/*
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* Workaround for ARM errata # 799270
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* Ensure that the L2 logic has been used within the previous 256 cycles
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* before modifying the ACTLR.SMP bit. This is required during boot before
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* MMU has been enabled, or during a specified reset or power down sequence.
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*/
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static inline void v7_enable_smp(uint32_t address)
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{
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uint32_t temp, val;
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/* Read auxiliary control register */
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asm volatile ("mrc p15, 0, %0, c1, c0, 1\n\t" : "=r"(val));
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/* Enable SMP */
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val |= (1 << 6);
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/* Dummy read to assure L2 access */
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temp = readl(address);
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temp &= 0;
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val |= temp;
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/* Write auxiliary control register */
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asm volatile ("mcr p15, 0, %0, c1, c0, 1\n\t" : : "r"(val));
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CP15DSB;
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CP15ISB;
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}
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void v7_en_l2_hazard_detect(void);
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void v7_outer_cache_enable(void);
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void v7_outer_cache_disable(void);
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void v7_outer_cache_flush_all(void);
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void v7_outer_cache_inval_all(void);
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void v7_outer_cache_flush_range(u32 start, u32 end);
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void v7_outer_cache_inval_range(u32 start, u32 end);
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#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
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int armv7_init_nonsec(void);
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bool armv7_boot_nonsec(void);
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/* defined in assembly file */
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unsigned int _nonsec_init(void);
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void _do_nonsec_entry(void *target_pc, unsigned long r0,
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unsigned long r1, unsigned long r2);
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void _smp_pen(void);
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extern char __secure_start[];
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extern char __secure_end[];
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#endif /* CONFIG_ARMV7_NONSEC || CONFIG_ARMV7_VIRT */
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void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr,
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u32 cpu_rev_comb, u32 cpu_variant,
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u32 cpu_rev);
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#endif /* ! __ASSEMBLY__ */
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#endif
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