u-boot-brain/arch/arm/mach-socfpga
Marek Vasut c5f4b80575 ARM: socfpga: Remove socfpga_sdram_apply_static_cfg()
The usage of socfpga_sdram_apply_static_cfg() seems rather dubious and
is confirmed to lead to a rare system hang when enabling bridges. This
patch removes the socfpga_sdram_apply_static_cfg() altogether, because
it's use seems unjustified and problematic.

The socfpga_sdram_apply_static_cfg() triggers write to SDRAM staticcfg
register to set the applycfg bit, which according to old vendor U-Boot
sources can only be written when there is no traffic between the SDRAM
controller and the rest of the system. Empirical measurements confirm
this, setting the applycfg bit when there is traffic between the SDRAM
controller and CPU leads to the SDRAM controller accesses being blocked
shortly after.

Altera originally solved this by moving the entire code which sets the
staticcfg register to OCRAM [1]. The commit message claims that the
applycfg bit needs to be set after write to fpgaportrst register. This
is however inverted by Altera shortly after in [2], where the order
becomes the exact opposite of what commit message [1] claims to be the
required order. The explanation points to a possible problem in AMP
use-case, where the FPGA might be sending transactions through the F2S
bridge.

However, the AMP is only the tip of the iceberg here. Any of the other
L2, L3 or L4 masters can trigger transactions to the SDRAM. It becomes
rather non-trivial to guarantee there are no transactions to the SDRAM
controller.

The SoCFPGA SDRAM driver always writes the applycfg bit in SPL. Thus,
writing the applycfg again in bridge enable code seems redundant and
can presumably be dropped.

[1] 75905816ec
[2] 8ba6986b04

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
2019-04-29 10:33:45 +02:00
..
include/mach ARM: socfpga: Add support for selecting bridges in bridge command 2019-04-29 10:08:56 +02:00
board.c ARM: socfpga: Reorder Arria10 SPL 2018-08-24 12:05:20 +02:00
clock_manager_arria10.c ARM: socfpga: Reorder Arria10 SPL 2018-08-24 12:05:20 +02:00
clock_manager_gen5.c SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
clock_manager_s10.c arm: socfpga: stratix10: Add clock manager driver for Stratix10 SoC 2018-05-18 10:30:47 +02:00
clock_manager.c ARM: socfpga: clk: Make L4SP and MMC clock calculation Gen5 only 2018-08-13 22:35:42 +02:00
fpga_manager.c SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
freeze_controller.c SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
Kconfig arm: socfpga: gen5: reduce SPL pre-reloc malloc 2019-04-25 00:00:49 +02:00
mailbox_s10.c arm: socfpga: mailbox: Fix off-by-one error on command length checking 2019-04-25 00:00:49 +02:00
Makefile ARM: socfpga: Convert Arria10 to timer framework 2018-08-24 12:05:20 +02:00
misc_arria10.c ARM: socfpga: Add support for selecting bridges in bridge command 2019-04-29 10:08:56 +02:00
misc_gen5.c ARM: socfpga: Remove socfpga_sdram_apply_static_cfg() 2019-04-29 10:33:45 +02:00
misc_s10.c ARM: socfpga: Add support for selecting bridges in bridge command 2019-04-29 10:08:56 +02:00
misc.c ARM: socfpga: Add support for selecting bridges in bridge command 2019-04-29 10:08:56 +02:00
mmu-arm64_s10.c arm: socfpga: stratix10: Add MMU support for Stratix10 SoC 2018-07-12 09:22:11 +02:00
pinmux_arria10.c SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
qts-filter.sh SPDX: Convert a few files that were missed before 2018-05-10 20:38:35 -04:00
reset_manager_arria10.c ARM: socfpga: Zap unused reset code 2018-08-13 22:35:42 +02:00
reset_manager_gen5.c ARM: socfpga: Fully unmap the FPGA bridges from L3 space 2019-04-29 10:08:55 +02:00
reset_manager_s10.c arm: socfpga: stratix10: Add cpu_has_been_warmreset() 2019-04-17 22:20:17 +02:00
reset_manager.c arm: socfpga: stratix10: Add reset manager driver for Stratix10 SoC 2018-05-18 10:30:47 +02:00
scan_manager.c SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
spl_a10.c ARM: socfpga: Disable D cache in SPL 2019-03-09 17:59:13 +01:00
spl_gen5.c ARM: socfpga: Disable bridges in SPL unless booting from FPGA 2019-04-29 10:08:55 +02:00
spl_s10.c ddr: altera: stratix10: Move SDRAM size check to SDRAM driver 2019-04-17 22:20:17 +02:00
system_manager_gen5.c SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
system_manager_s10.c arm: socfpga: stratix10: Add pinmux support for Stratix10 SoC 2018-05-18 10:30:48 +02:00
timer_s10.c arm: socfpga: stratix10: Add timer support for Stratix10 SoC 2018-07-12 09:22:12 +02:00
timer.c SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
wrap_iocsr_config.c SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
wrap_pinmux_config_s10.c arm: socfpga: stratix10: Add pinmux support for Stratix10 SoC 2018-05-18 10:30:48 +02:00
wrap_pinmux_config.c SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
wrap_pll_config_s10.c arm: socfpga: stratix10: Add clock manager driver for Stratix10 SoC 2018-05-18 10:30:47 +02:00
wrap_pll_config.c SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
wrap_sdram_config.c arm: socfpga: make config structs const 2018-11-29 12:45:15 +01:00