mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-01 15:53:46 +09:00
c5437e5b8a
According to the Cortex-A7 TRM, for ACTLR.SMP bit "You must ensure this bit is set to 1 before the caches and MMU are enabled, or any cache and TLB maintenance operations are performed". ROM sets this bit in normal boot flow, but when in serial download mode, it is not set. Here we add it in u-boot as a common flow for all i.MX cortex-a7 platforms, including mx7d, mx6ul/ull and mx7ulp. Signed-off-by: Ye Li <ye.li@nxp.com> [fabio: adapted to U-Boot mainline codebase and make checkpatch happy] Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
296 lines
7.3 KiB
C
296 lines
7.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2015 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/mach-imx/boot_mode.h>
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#include <asm/mach-imx/dma.h>
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#include <asm/mach-imx/hab.h>
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#include <asm/mach-imx/rdc-sema.h>
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#include <asm/arch/imx-rdc.h>
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#include <asm/arch/crm_regs.h>
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#include <dm.h>
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#include <imx_thermal.h>
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#include <fsl_sec.h>
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#include <asm/setup.h>
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#if defined(CONFIG_IMX_THERMAL)
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static const struct imx_thermal_plat imx7_thermal_plat = {
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.regs = (void *)ANATOP_BASE_ADDR,
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.fuse_bank = 3,
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.fuse_word = 3,
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};
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U_BOOT_DEVICE(imx7_thermal) = {
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.name = "imx_thermal",
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.platdata = &imx7_thermal_plat,
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};
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#endif
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#if CONFIG_IS_ENABLED(IMX_RDC)
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/*
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* In current design, if any peripheral was assigned to both A7 and M4,
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* it will receive ipg_stop or ipg_wait when any of the 2 platforms enter
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* low power mode. So M4 sleep will cause some peripherals fail to work
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* at A7 core side. At default, all resources are in domain 0 - 3.
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*
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* There are 26 peripherals impacted by this IC issue:
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* SIM2(sim2/emvsim2)
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* SIM1(sim1/emvsim1)
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* UART1/UART2/UART3/UART4/UART5/UART6/UART7
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* SAI1/SAI2/SAI3
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* WDOG1/WDOG2/WDOG3/WDOG4
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* GPT1/GPT2/GPT3/GPT4
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* PWM1/PWM2/PWM3/PWM4
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* ENET1/ENET2
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* Software Workaround:
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* Here we setup some resources to domain 0 where M4 codes will move
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* the M4 out of this domain. Then M4 is not able to access them any longer.
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* This is a workaround for ic issue. So the peripherals are not shared
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* by them. This way requires the uboot implemented the RDC driver and
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* set the 26 IPs above to domain 0 only. M4 code will assign resource
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* to its own domain, if it want to use the resource.
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*/
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static rdc_peri_cfg_t const resources[] = {
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(RDC_PER_SIM1 | RDC_DOMAIN(0)),
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(RDC_PER_SIM2 | RDC_DOMAIN(0)),
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(RDC_PER_UART1 | RDC_DOMAIN(0)),
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(RDC_PER_UART2 | RDC_DOMAIN(0)),
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(RDC_PER_UART3 | RDC_DOMAIN(0)),
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(RDC_PER_UART4 | RDC_DOMAIN(0)),
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(RDC_PER_UART5 | RDC_DOMAIN(0)),
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(RDC_PER_UART6 | RDC_DOMAIN(0)),
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(RDC_PER_UART7 | RDC_DOMAIN(0)),
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(RDC_PER_SAI1 | RDC_DOMAIN(0)),
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(RDC_PER_SAI2 | RDC_DOMAIN(0)),
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(RDC_PER_SAI3 | RDC_DOMAIN(0)),
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(RDC_PER_WDOG1 | RDC_DOMAIN(0)),
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(RDC_PER_WDOG2 | RDC_DOMAIN(0)),
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(RDC_PER_WDOG3 | RDC_DOMAIN(0)),
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(RDC_PER_WDOG4 | RDC_DOMAIN(0)),
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(RDC_PER_GPT1 | RDC_DOMAIN(0)),
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(RDC_PER_GPT2 | RDC_DOMAIN(0)),
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(RDC_PER_GPT3 | RDC_DOMAIN(0)),
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(RDC_PER_GPT4 | RDC_DOMAIN(0)),
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(RDC_PER_PWM1 | RDC_DOMAIN(0)),
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(RDC_PER_PWM2 | RDC_DOMAIN(0)),
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(RDC_PER_PWM3 | RDC_DOMAIN(0)),
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(RDC_PER_PWM4 | RDC_DOMAIN(0)),
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(RDC_PER_ENET1 | RDC_DOMAIN(0)),
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(RDC_PER_ENET2 | RDC_DOMAIN(0)),
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};
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static void isolate_resource(void)
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{
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imx_rdc_setup_peripherals(resources, ARRAY_SIZE(resources));
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}
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#endif
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#if defined(CONFIG_SECURE_BOOT)
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struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
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.bank = 1,
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.word = 3,
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};
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#endif
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static bool is_mx7d(void)
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{
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struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
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struct fuse_bank *bank = &ocotp->bank[1];
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struct fuse_bank1_regs *fuse =
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(struct fuse_bank1_regs *)bank->fuse_regs;
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int val;
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val = readl(&fuse->tester4);
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if (val & 1)
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return false;
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else
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return true;
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}
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u32 get_cpu_rev(void)
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{
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struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *)
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ANATOP_BASE_ADDR;
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u32 reg = readl(&ccm_anatop->digprog);
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u32 type = (reg >> 16) & 0xff;
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if (!is_mx7d())
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type = MXC_CPU_MX7S;
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reg &= 0xff;
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return (type << 12) | reg;
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}
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#ifdef CONFIG_REVISION_TAG
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u32 __weak get_board_rev(void)
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{
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return get_cpu_rev();
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}
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#endif
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/* enable all periherial can be accessed in nosec mode */
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static void init_csu(void)
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{
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int i = 0;
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for (i = 0; i < CSU_NUM_REGS; i++)
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writel(CSU_INIT_SEC_LEVEL0, CSU_IPS_BASE_ADDR + i * 4);
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}
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static void imx_enet_mdio_fixup(void)
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{
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struct iomuxc_gpr_base_regs *gpr_regs =
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(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
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/*
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* The management data input/output (MDIO) requires open-drain,
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* i.MX7D TO1.0 ENET MDIO pin has no open drain, but TO1.1 supports
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* this feature. So to TO1.1, need to enable open drain by setting
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* bits GPR0[8:7].
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*/
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if (soc_rev() >= CHIP_REV_1_1) {
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setbits_le32(&gpr_regs->gpr[0],
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IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_MASK);
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}
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}
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int arch_cpu_init(void)
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{
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init_aips();
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init_csu();
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/* Disable PDE bit of WMCR register */
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imx_wdog_disable_powerdown();
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imx_enet_mdio_fixup();
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#ifdef CONFIG_APBH_DMA
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/* Start APBH DMA */
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mxs_dma_init();
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#endif
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#if CONFIG_IS_ENABLED(IMX_RDC)
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isolate_resource();
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#endif
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init_snvs();
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return 0;
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}
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#ifdef CONFIG_ARCH_MISC_INIT
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int arch_misc_init(void)
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{
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#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
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if (is_mx7d())
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env_set("soc", "imx7d");
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else
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env_set("soc", "imx7s");
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#endif
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#ifdef CONFIG_FSL_CAAM
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sec_init();
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#endif
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return 0;
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}
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#endif
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#ifdef CONFIG_SERIAL_TAG
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/*
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* OCOTP_TESTER
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* i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1, 08/2016
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* OCOTP_TESTER describes a unique ID based on silicon wafer
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* and die X/Y position
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*
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* OCOTOP_TESTER offset 0x410
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* 31:0 fuse 0
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* FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID
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*
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* OCOTP_TESTER1 offset 0x420
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* 31:24 fuse 1
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* The X-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID
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* 23:16 fuse 1
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* The Y-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID
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* 15:11 fuse 1
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* The wafer number of the wafer on which the device was fabricated/SJC
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* CHALLENGE/ Unique ID
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* 10:0 fuse 1
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* FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID
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*/
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void get_board_serial(struct tag_serialnr *serialnr)
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{
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struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
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struct fuse_bank *bank = &ocotp->bank[0];
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struct fuse_bank0_regs *fuse =
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(struct fuse_bank0_regs *)bank->fuse_regs;
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serialnr->low = fuse->tester0;
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serialnr->high = fuse->tester1;
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}
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#endif
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void set_wdog_reset(struct wdog_regs *wdog)
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{
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u32 reg = readw(&wdog->wcr);
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/*
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* Output WDOG_B signal to reset external pmic or POR_B decided by
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* the board desgin. Without external reset, the peripherals/DDR/
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* PMIC are not reset, that may cause system working abnormal.
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*/
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reg = readw(&wdog->wcr);
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reg |= 1 << 3;
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/*
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* WDZST bit is write-once only bit. Align this bit in kernel,
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* otherwise kernel code will have no chance to set this bit.
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*/
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reg |= 1 << 0;
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writew(reg, &wdog->wcr);
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}
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/*
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* cfg_val will be used for
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* Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
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* After reset, if GPR10[28] is 1, ROM will copy GPR9[25:0]
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* to SBMR1, which will determine the boot device.
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*/
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const struct boot_mode soc_boot_modes[] = {
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{"ecspi1:0", MAKE_CFGVAL(0x00, 0x60, 0x00, 0x00)},
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{"ecspi1:1", MAKE_CFGVAL(0x40, 0x62, 0x00, 0x00)},
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{"ecspi1:2", MAKE_CFGVAL(0x80, 0x64, 0x00, 0x00)},
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{"ecspi1:3", MAKE_CFGVAL(0xc0, 0x66, 0x00, 0x00)},
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{"weim", MAKE_CFGVAL(0x00, 0x50, 0x00, 0x00)},
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{"qspi1", MAKE_CFGVAL(0x10, 0x40, 0x00, 0x00)},
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/* 4 bit bus width */
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{"usdhc1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)},
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{"usdhc2", MAKE_CFGVAL(0x10, 0x14, 0x00, 0x00)},
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{"usdhc3", MAKE_CFGVAL(0x10, 0x18, 0x00, 0x00)},
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{"mmc1", MAKE_CFGVAL(0x10, 0x20, 0x00, 0x00)},
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{"mmc2", MAKE_CFGVAL(0x10, 0x24, 0x00, 0x00)},
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{"mmc3", MAKE_CFGVAL(0x10, 0x28, 0x00, 0x00)},
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{NULL, 0},
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};
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void s_init(void)
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{
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/* clock configuration. */
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clock_init();
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return;
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}
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void reset_misc(void)
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{
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#ifdef CONFIG_VIDEO_MXS
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lcdif_power_down();
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#endif
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}
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